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hw/p*: pass owner to memory_region_init* functions

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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2013-06-06 21:25:08 -04:00
parent eedfac6f38
commit 40c5dce99b
21 changed files with 91 additions and 86 deletions
Download patch file Download diff file Expand all files Collapse all files

6
hw/pci/msix.c
View file

@ -280,10 +280,10 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries,
msix_mask_all(dev, nentries);
memory_region_init_io(&dev->msix_table_mmio, NULL, &msix_table_mmio_ops, dev,
memory_region_init_io(&dev->msix_table_mmio, OBJECT(dev), &msix_table_mmio_ops, dev,
"msix-table", table_size);
memory_region_add_subregion(table_bar, table_offset, &dev->msix_table_mmio);
memory_region_init_io(&dev->msix_pba_mmio, NULL, &msix_pba_mmio_ops, dev,
memory_region_init_io(&dev->msix_pba_mmio, OBJECT(dev), &msix_pba_mmio_ops, dev,
"msix-pba", pba_size);
memory_region_add_subregion(pba_bar, pba_offset, &dev->msix_pba_mmio);
@ -311,7 +311,7 @@ int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,
}
name = g_strdup_printf("%s-msix", dev->name);
memory_region_init(&dev->msix_exclusive_bar, NULL, name, MSIX_EXCLUSIVE_BAR_SIZE);
memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev), name, MSIX_EXCLUSIVE_BAR_SIZE);
g_free(name);
ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr,

5
hw/pci/pci.c
View file

@ -811,7 +811,8 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
dma_as = &address_space_memory;
}
memory_region_init_alias(&pci_dev->bus_master_enable_region, NULL, "bus master",
memory_region_init_alias(&pci_dev->bus_master_enable_region,
OBJECT(pci_dev), "bus master",
dma_as->root, 0, memory_region_size(dma_as->root));
memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region,
@ -1945,7 +1946,7 @@ static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
}
pdev->has_rom = true;
memory_region_init_ram(&pdev->rom, NULL, name, size);
memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size);
vmstate_register_ram(&pdev->rom, &pdev->qdev);
ptr = memory_region_get_ram_ptr(&pdev->rom);
load_image(path, ptr);

12
hw/pci/pci_bridge.c
View file

@ -147,7 +147,7 @@ static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias,
* Apparently no way to do this with existing memory APIs. */
pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0;
memory_region_init_alias(alias, NULL, name, space, base, size);
memory_region_init_alias(alias, OBJECT(bridge), name, space, base, size);
memory_region_add_subregion_overlap(parent_space, base, alias, 1);
}
@ -156,13 +156,13 @@ static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent,
{
uint16_t brctl = pci_get_word(br->dev.config + PCI_BRIDGE_CONTROL);
memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], NULL,
memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br),
"pci_bridge_vga_io_lo", &br->address_space_io,
QEMU_PCI_VGA_IO_LO_BASE, QEMU_PCI_VGA_IO_LO_SIZE);
memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI], NULL,
memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI], OBJECT(br),
"pci_bridge_vga_io_hi", &br->address_space_io,
QEMU_PCI_VGA_IO_HI_BASE, QEMU_PCI_VGA_IO_HI_SIZE);
memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM], NULL,
memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM], OBJECT(br),
"pci_bridge_vga_mem", &br->address_space_mem,
QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE);
@ -367,9 +367,9 @@ int pci_bridge_initfn(PCIDevice *dev, const char *typename)
sec_bus->parent_dev = dev;
sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
sec_bus->address_space_mem = &br->address_space_mem;
memory_region_init(&br->address_space_mem, NULL, "pci_bridge_pci", INT64_MAX);
memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", INT64_MAX);
sec_bus->address_space_io = &br->address_space_io;
memory_region_init(&br->address_space_io, NULL, "pci_bridge_io", 65536);
memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io", 65536);
br->windows = pci_bridge_region_init(br);
QLIST_INIT(&sec_bus->child);
QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);

3
hw/pci/pcie_host.c
View file

@ -130,7 +130,8 @@ void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr,
assert(size >= PCIE_MMCFG_SIZE_MIN);
assert(size <= PCIE_MMCFG_SIZE_MAX);
e->size = size;
memory_region_init_io(&e->mmio, NULL, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size);
memory_region_init_io(&e->mmio, OBJECT(e), &pcie_mmcfg_ops, e,
"pcie-mmcfg", e->size);
e->base_addr = addr;
memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio);
}

4
hw/pci/shpc.c
View file

@ -612,8 +612,8 @@ int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset)
}
/* TODO: init cmask */
memory_region_init_io(&shpc->mmio, NULL, &shpc_mmio_ops, d, "shpc-mmio",
SHPC_SIZEOF(d));
memory_region_init_io(&shpc->mmio, OBJECT(d), &shpc_mmio_ops,
d, "shpc-mmio", SHPC_SIZEOF(d));
shpc_cap_update_dword(d);
memory_region_add_subregion(bar, offset, &shpc->mmio);
pci_bus_hotplug(sec_bus, shpc_device_hotplug, &d->qdev);