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Revert "exec.c: Fix breakpoint invalidation race"

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Now that we have proper locking after MTTCG patches have landed, we
can revert the commit.  This reverts commit

a9353fe897.

CC: Peter Maydell <peter.maydell@linaro.org>
CC: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Message-Id: <20170712215143.19594-1-bobby.prani@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Pranith Kumar 2017-07-12 17:51:42 -04:00 • committed by Paolo Bonzini
parent 04bf2526ce
commit 406bc339b0
2 changed files with 22 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

25
exec.c
View file

@ -775,15 +775,28 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
#endif #endif
} }
#if defined(CONFIG_USER_ONLY)
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
{ {
/* Flush the whole TB as this will not have race conditions mmap_lock();
* even if we don't have proper locking yet. tb_lock();
* Ideally we would just invalidate the TBs for the tb_invalidate_phys_page_range(pc, pc + 1, 0);
* specified PC. tb_unlock();
*/ mmap_unlock();
tb_flush(cpu);
} }
#else
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
{
MemTxAttrs attrs;
hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
int asidx = cpu_asidx_from_attrs(cpu, attrs);
if (phys != -1) {
/* Locks grabbed by tb_invalidate_phys_addr */
tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
phys | (pc & ~TARGET_PAGE_MASK));
}
}
#endif
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
void cpu_watchpoint_remove_all(CPUState *cpu, int mask) void cpu_watchpoint_remove_all(CPUState *cpu, int mask)

3
include/exec/exec-all.h
View file

@ -290,6 +290,9 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
uint16_t idxmap) uint16_t idxmap)
{ {
} }
static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
{
}
#endif #endif
#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */