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target-ppc: Model SPE floating-point instructions more accurately
Single-precision and double-precision floating-point instructions should be separated into their own categories, since some chips only support single-precision instructions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6575 c046a42c-6fe2-441c-8c8c-71466251a162
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2 changed files with 57 additions and 55 deletions
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@ -3984,7 +3984,7 @@ static void init_proc_G2LE (CPUPPCState *env)
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* all SPE multiply-accumulate instructions
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*/
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#define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
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PPC_SPE | PPC_SPEFPU | \
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PPC_SPE | PPC_SPE_SINGLE | \
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PPC_WRTEE | PPC_RFDI | \
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PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
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PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
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@ -4147,13 +4147,13 @@ static void init_proc_e300 (CPUPPCState *env)
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ppc6xx_irq_init(env);
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}
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/* e500 core */
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#define POWERPC_INSNS_e500 (PPC_INSNS_BASE | PPC_ISEL | \
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PPC_SPE | PPC_SPEFPU | \
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PPC_WRTEE | PPC_RFDI | \
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PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
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PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
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PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
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/* e500 core */
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#define POWERPC_INSNS_e500 (PPC_INSNS_BASE | PPC_ISEL | \
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PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
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PPC_WRTEE | PPC_RFDI | \
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PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
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PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
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PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
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PPC_BOOKE)
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#define POWERPC_MSRM_e500 (0x000000000606FF30ULL)
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#define POWERPC_MMU_e500 (POWERPC_MMU_BOOKE_FSL)
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@ -9431,7 +9431,7 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
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gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
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34, "power-altivec.xml", 0);
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}
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if ((def->insns_flags & PPC_SPE) | (def->insns_flags & PPC_SPEFPU)) {
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if (def->insns_flags & PPC_SPE) {
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gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
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34, "power-spe.xml", 0);
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}
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