motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-08 18:23:57 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_DISABLE_PCIE_BIT definition

Browse source 
PVSCSI_COMPAT_DISABLE_PCIE_BIT was only used by the
hw_compat_2_5[] array, via the 'x-disable-pcie=on' property.
We removed all machines using that array, lets remove all the
code around PVSCSI_COMPAT_DISABLE_PCIE_BIT, including the now
unused PVSCSIState::compat_flags field.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20250512083948.39294-16-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Philippe Mathieu-Daudé 2025-05-12 10:39:44 +02:00 • committed by Thomas Huth
parent 16c04166ae
commit 404b27b739
1 changed files with 1 additions and 29 deletions
Download patch file Download diff file Expand all files Collapse all files

30
hw/scsi/vmw_pvscsi.c
View file

@ -68,11 +68,6 @@ struct PVSCSIClass {
OBJECT_DECLARE_TYPE(PVSCSIState, PVSCSIClass, PVSCSI)
/* Compatibility flags for migration */
#define PVSCSI_COMPAT_DISABLE_PCIE_BIT 1
#define PVSCSI_COMPAT_DISABLE_PCIE \
(1 << PVSCSI_COMPAT_DISABLE_PCIE_BIT)
#define PVSCSI_MSI_OFFSET (0x7c)
#define PVSCSI_EXP_EP_OFFSET (0x40)
@ -123,8 +118,6 @@ struct PVSCSIState {
uint8_t msi_used; /* For migration compatibility */
PVSCSIRingInfo rings; /* Data transfer rings manager */
uint32_t resetting; /* Reset in progress */
uint32_t compat_flags;
};
typedef struct PVSCSIRequest {
@ -1224,21 +1217,8 @@ pvscsi_post_load(void *opaque, int version_id)
return 0;
}
static bool pvscsi_vmstate_need_pcie_device(void *opaque)
{
PVSCSIState *s = PVSCSI(opaque);
return !(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE);
}
static bool pvscsi_vmstate_test_pci_device(void *opaque, int version_id)
{
return !pvscsi_vmstate_need_pcie_device(opaque);
}
static const VMStateDescription vmstate_pvscsi_pcie_device = {
.name = "pvscsi/pcie",
.needed = pvscsi_vmstate_need_pcie_device,
.fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, PVSCSIState),
VMSTATE_END_OF_LIST()
@ -1252,9 +1232,6 @@ static const VMStateDescription vmstate_pvscsi = {
.pre_save = pvscsi_pre_save,
.post_load = pvscsi_post_load,
.fields = (const VMStateField[]) {
VMSTATE_STRUCT_TEST(parent_obj, PVSCSIState,
pvscsi_vmstate_test_pci_device, 0,
vmstate_pci_device, PCIDevice),
VMSTATE_UINT8(msi_used, PVSCSIState),
VMSTATE_UINT32(resetting, PVSCSIState),
VMSTATE_UINT64(reg_interrupt_status, PVSCSIState),
@ -1288,19 +1265,14 @@ static const VMStateDescription vmstate_pvscsi = {
static const Property pvscsi_properties[] = {
DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1),
DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags,
PVSCSI_COMPAT_DISABLE_PCIE_BIT, false),
};
static void pvscsi_realize(DeviceState *qdev, Error **errp)
{
PVSCSIClass *pvs_c = PVSCSI_GET_CLASS(qdev);
PCIDevice *pci_dev = PCI_DEVICE(qdev);
PVSCSIState *s = PVSCSI(qdev);
if (!(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE)) {
pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
}
pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
pvs_c->parent_dc_realize(qdev, errp);
}