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target-arm queue:

Browse source 
* hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
  * versal: Add the Cortex-R5s in the Real-Time Processing Unit (RPU) subsystem
  * versal: model enough of the Clock/Reset Low-power domain (CRL) to allow control of the Cortex-R5s
  * xlnx-zynqmp: Connect 4 TTC timers
  * exynos4210: Refactor GIC/combiner code to stop using qemu_split_irq
  * realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
  * stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
  * hw/core/irq: remove unused 'qemu_irq_split' function
  * npcm7xx: use symbolic constants for PWRON STRAP bit fields
  * virt: document impact of gic-version on max CPUs
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 =Rke9
 -----END PGP SIGNATURE-----

Merge tag 'pull-target-arm-20220421' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
 * versal: Add the Cortex-R5s in the Real-Time Processing Unit (RPU) subsystem
 * versal: model enough of the Clock/Reset Low-power domain (CRL) to allow control of the Cortex-R5s
 * xlnx-zynqmp: Connect 4 TTC timers
 * exynos4210: Refactor GIC/combiner code to stop using qemu_split_irq
 * realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
 * stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
 * hw/core/irq: remove unused 'qemu_irq_split' function
 * npcm7xx: use symbolic constants for PWRON STRAP bit fields
 * virt: document impact of gic-version on max CPUs

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# =Rke9
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 21 Apr 2022 04:16:53 AM PDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]

* tag 'pull-target-arm-20220421' of https://git.linaro.org/people/pmaydell/qemu-arm: (31 commits)
  hw/arm: Use bit fields for NPCM7XX PWRON STRAPs
  hw/misc: Add PWRON STRAP bit fields in GCR module
  hw/arm/virt: impact of gic-version on max CPUs
  hw/core/irq: remove unused 'qemu_irq_split' function
  hw/arm/stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
  hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
  hw/arm/exynos4210: Drop Exynos4210Irq struct
  hw/arm/exynos4210: Put combiners into state struct
  hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs()
  hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs
  hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners
  hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines
  hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs()
  hw/arm/exynos4210: Delete unused macro definitions
  hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c
  hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct
  hw/arm/exynos4210: Put external GIC into state struct
  hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c
  hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[]
  hw/arm/exynos4210: Coalesce board_irqs and irq_table
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-21 08:04:43 -07:00
commit 401d467894
25 changed files with 1457 additions and 600 deletions
Download patch file Download diff file Expand all files Collapse all files

50
include/hw/arm/exynos4210.h
View file

@ -26,6 +26,10 @@
#include "hw/or-irq.h"
#include "hw/sysbus.h"
#include "hw/cpu/a9mpcore.h"
#include "hw/intc/exynos4210_gic.h"
#include "hw/intc/exynos4210_combiner.h"
#include "hw/core/split-irq.h"
#include "target/arm/cpu-qom.h"
#include "qom/object.h"
@ -65,34 +69,25 @@
#define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \
(EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit))
#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8)
#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
/* IRQs number for external and internal GIC */
#define EXYNOS4210_EXT_GIC_NIRQ (160-32)
#define EXYNOS4210_INT_GIC_NIRQ 64
#define EXYNOS4210_I2C_NUMBER 9
#define EXYNOS4210_NUM_DMA 3
typedef struct Exynos4210Irq {
qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ];
qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
} Exynos4210Irq;
/*
* We need one splitter for every external combiner input, plus
* one for every non-zero entry in combiner_grp_to_gic_id[],
* minus one for every external combiner ID in second or later
* places in a combinermap[] line.
* We'll assert in exynos4210_init_board_irqs() if this is wrong.
*/
#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38)
struct Exynos4210State {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
ARMCPU *cpu[EXYNOS4210_NCPUS];
Exynos4210Irq irqs;
qemu_irq *irq_table;
qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
MemoryRegion chipid_mem;
MemoryRegion iram_mem;
@ -102,6 +97,12 @@ struct Exynos4210State {
MemoryRegion bootreg_mem;
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
A9MPPrivState a9mpcore;
Exynos4210GicState ext_gic;
Exynos4210CombinerState int_combiner;
Exynos4210CombinerState ext_combiner;
SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS];
};
#define TYPE_EXYNOS4210_SOC "exynos4210"
@ -110,25 +111,12 @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
void exynos4210_write_secondary(ARMCPU *cpu,
const struct arm_boot_info *info);
/* Initialize exynos4210 IRQ subsystem stub */
qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
/* Initialize board IRQs.
* These IRQs contain splitted Int/External Combiner and External Gic IRQs */
void exynos4210_init_board_irqs(Exynos4210Irq *s);
/* Get IRQ number from exynos4210 IRQ subsystem stub.
* To identify IRQ source use internal combiner group and bit number
* grp - group number
* bit - bit number inside group */
uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit);
/*
* Get Combiner input GPIO into irqs structure
*/
void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
int ext);
/*
* exynos4210 UART
*/

16
include/hw/arm/xlnx-versal.h
View file

@ -14,6 +14,7 @@
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
#include "hw/cpu/cluster.h"
#include "hw/or-irq.h"
#include "hw/sd/sdhci.h"
#include "hw/intc/arm_gicv3.h"
@ -28,12 +29,14 @@
#include "hw/nvram/xlnx-versal-efuse.h"
#include "hw/ssi/xlnx-versal-ospi.h"
#include "hw/dma/xlnx_csu_dma.h"
#include "hw/misc/xlnx-versal-crl.h"
#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
#define XLNX_VERSAL_NR_ACPUS 2
#define XLNX_VERSAL_NR_RCPUS 2
#define XLNX_VERSAL_NR_UARTS 2
#define XLNX_VERSAL_NR_GEMS 2
#define XLNX_VERSAL_NR_ADMAS 8
@ -49,6 +52,7 @@ struct Versal {
struct {
struct {
MemoryRegion mr;
CPUClusterState cluster;
ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
GICv3State gic;
} apu;
@ -71,10 +75,21 @@ struct Versal {
VersalUsb2 usb;
} iou;
/* Real-time Processing Unit. */
struct {
MemoryRegion mr;
MemoryRegion mr_ps_alias;
CPUClusterState cluster;
ARMCPU cpu[XLNX_VERSAL_NR_RCPUS];
} rpu;
struct {
qemu_or_irq irq_orgate;
XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
} xram;
XlnxVersalCRL crl;
} lpd;
/* The Platform Management Controller subsystem. */
@ -115,6 +130,7 @@ struct Versal {
#define VERSAL_TIMER_NS_EL1_IRQ 14
#define VERSAL_TIMER_NS_EL2_IRQ 10
#define VERSAL_CRL_IRQ 10
#define VERSAL_UART0_IRQ_0 18
#define VERSAL_UART1_IRQ_0 19
#define VERSAL_USB0_IRQ_0 22

4
include/hw/arm/xlnx-zynqmp.h
View file

@ -41,6 +41,7 @@
#include "hw/or-irq.h"
#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
#include "hw/misc/xlnx-zynqmp-crf.h"
#include "hw/timer/cadence_ttc.h"
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@ -84,6 +85,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
#define XLNX_ZYNQMP_NUM_TTC 4
/*
* Unimplemented mmio regions needed to boot some images.
*/
@ -128,6 +131,7 @@ struct XlnxZynqMPState {
qemu_or_irq qspi_irq_orgate;
XlnxZynqMPAPUCtrl apu_ctrl;
XlnxZynqMPCRF crf;
CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
char *boot_cpu;
ARMCPU *boot_cpu_ptr;

57
include/hw/intc/exynos4210_combiner.h Normal file
View file

@ -0,0 +1,57 @@
/*
* Samsung exynos4210 Interrupt Combiner
*
* Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
* All rights reserved.
*
* Evgeny Voevodin <e.voevodin@samsung.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_INTC_EXYNOS4210_COMBINER
#define HW_INTC_EXYNOS4210_COMBINER
#include "hw/sysbus.h"
/*
* State for each output signal of internal combiner
*/
typedef struct CombinerGroupState {
uint8_t src_mask; /* 1 - source enabled, 0 - disabled */
uint8_t src_pending; /* Pending source interrupts before masking */
} CombinerGroupState;
#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER)
/* Number of groups and total number of interrupts for the internal combiner */
#define IIC_NGRP 64
#define IIC_NIRQ (IIC_NGRP * 8)
#define IIC_REGSET_SIZE 0x41
struct Exynos4210CombinerState {
SysBusDevice parent_obj;
MemoryRegion iomem;
struct CombinerGroupState group[IIC_NGRP];
uint32_t reg_set[IIC_REGSET_SIZE];
uint32_t icipsr[2];
uint32_t external; /* 1 means that this combiner is external */
qemu_irq output_irq[IIC_NGRP];
};
#endif

43
include/hw/intc/exynos4210_gic.h Normal file
View file

@ -0,0 +1,43 @@
/*
* Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c
*
* Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
* All rights reserved.
*
* Evgeny Voevodin <e.voevodin@samsung.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_INTC_EXYNOS4210_GIC_H
#define HW_INTC_EXYNOS4210_GIC_H
#include "hw/sysbus.h"
#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
#define EXYNOS4210_GIC_NCPUS 2
struct Exynos4210GicState {
SysBusDevice parent_obj;
MemoryRegion cpu_container;
MemoryRegion dist_container;
MemoryRegion cpu_alias[EXYNOS4210_GIC_NCPUS];
MemoryRegion dist_alias[EXYNOS4210_GIC_NCPUS];
uint32_t num_cpu;
DeviceState *gic;
};
#endif

5
include/hw/irq.h
View file

@ -46,11 +46,6 @@ void qemu_free_irq(qemu_irq irq);
/* Returns a new IRQ with opposite polarity. */
qemu_irq qemu_irq_invert(qemu_irq irq);
/* Returns a new IRQ which feeds into both the passed IRQs.
* It's probably better to use the TYPE_SPLIT_IRQ device instead.
*/
qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
/* For internal use in qtest. Similar to qemu_irq_split, but operating
on an existing vector of qemu_irq. */
void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);

30
include/hw/misc/npcm7xx_gcr.h
View file

@ -19,6 +19,36 @@
#include "exec/memory.h"
#include "hw/sysbus.h"
/*
* NPCM7XX PWRON STRAP bit fields
* 12: SPI0 powered by VSBV3 at 1.8V
* 11: System flash attached to BMC
* 10: BSP alternative pins.
* 9:8: Flash UART command route enabled.
* 7: Security enabled.
* 6: HI-Z state control.
* 5: ECC disabled.
* 4: Reserved
* 3: JTAG2 enabled.
* 2:0: CPU and DRAM clock frequency.
*/
#define NPCM7XX_PWRON_STRAP_SPI0F18 BIT(12)
#define NPCM7XX_PWRON_STRAP_SFAB BIT(11)
#define NPCM7XX_PWRON_STRAP_BSPA BIT(10)
#define NPCM7XX_PWRON_STRAP_FUP(x) ((x) << 8)
#define FUP_NORM_UART2 3
#define FUP_PROG_UART3 2
#define FUP_PROG_UART2 1
#define FUP_NORM_UART3 0
#define NPCM7XX_PWRON_STRAP_SECEN BIT(7)
#define NPCM7XX_PWRON_STRAP_HIZ BIT(6)
#define NPCM7XX_PWRON_STRAP_ECC BIT(5)
#define NPCM7XX_PWRON_STRAP_RESERVE1 BIT(4)
#define NPCM7XX_PWRON_STRAP_J2EN BIT(3)
#define NPCM7XX_PWRON_STRAP_CKFRQ(x) (x)
#define CKFRQ_SKIPINIT 0x000
#define CKFRQ_DEFAULT 0x111
/*
* Number of registers in our device state structure. Don't change this without
* incrementing the version_id in the vmstate.

235
include/hw/misc/xlnx-versal-crl.h Normal file
View file

@ -0,0 +1,235 @@
/*
* QEMU model of the Clock-Reset-LPD (CRL).
*
* Copyright (c) 2022 Xilinx Inc.
* SPDX-License-Identifier: GPL-2.0-or-later
*
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
*/
#ifndef HW_MISC_XLNX_VERSAL_CRL_H
#define HW_MISC_XLNX_VERSAL_CRL_H
#include "hw/sysbus.h"
#include "hw/register.h"
#include "target/arm/cpu.h"
#define TYPE_XLNX_VERSAL_CRL "xlnx,versal-crl"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL)
REG32(ERR_CTRL, 0x0)
FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
REG32(IR_STATUS, 0x4)
FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
REG32(IR_MASK, 0x8)
FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
REG32(IR_ENABLE, 0xc)
FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
REG32(IR_DISABLE, 0x10)
FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
REG32(WPROT, 0x1c)
FIELD(WPROT, ACTIVE, 0, 1)
REG32(PLL_CLK_OTHER_DMN, 0x20)
FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1)
REG32(RPLL_CTRL, 0x40)
FIELD(RPLL_CTRL, POST_SRC, 24, 3)
FIELD(RPLL_CTRL, PRE_SRC, 20, 3)
FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2)
FIELD(RPLL_CTRL, FBDIV, 8, 8)
FIELD(RPLL_CTRL, BYPASS, 3, 1)
FIELD(RPLL_CTRL, RESET, 0, 1)
REG32(RPLL_CFG, 0x44)
FIELD(RPLL_CFG, LOCK_DLY, 25, 7)
FIELD(RPLL_CFG, LOCK_CNT, 13, 10)
FIELD(RPLL_CFG, LFHF, 10, 2)
FIELD(RPLL_CFG, CP, 5, 4)
FIELD(RPLL_CFG, RES, 0, 4)
REG32(RPLL_FRAC_CFG, 0x48)
FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1)
FIELD(RPLL_FRAC_CFG, SEED, 22, 3)
FIELD(RPLL_FRAC_CFG, ALGRTHM, 19, 1)
FIELD(RPLL_FRAC_CFG, ORDER, 18, 1)
FIELD(RPLL_FRAC_CFG, DATA, 0, 16)
REG32(PLL_STATUS, 0x50)
FIELD(PLL_STATUS, RPLL_STABLE, 2, 1)
FIELD(PLL_STATUS, RPLL_LOCK, 0, 1)
REG32(RPLL_TO_XPD_CTRL, 0x100)
FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1)
FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10)
REG32(LPD_TOP_SWITCH_CTRL, 0x104)
FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1)
FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1)
FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10)
FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3)
REG32(LPD_LSBUS_CTRL, 0x108)
FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1)
FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10)
FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3)
REG32(CPU_R5_CTRL, 0x10c)
FIELD(CPU_R5_CTRL, CLKACT_OCM2, 28, 1)
FIELD(CPU_R5_CTRL, CLKACT_OCM, 27, 1)
FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1)
FIELD(CPU_R5_CTRL, CLKACT, 25, 1)
FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10)
FIELD(CPU_R5_CTRL, SRCSEL, 0, 3)
REG32(IOU_SWITCH_CTRL, 0x114)
FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1)
FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10)
FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3)
REG32(GEM0_REF_CTRL, 0x118)
FIELD(GEM0_REF_CTRL, CLKACT_RX, 27, 1)
FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1)
FIELD(GEM0_REF_CTRL, CLKACT, 25, 1)
FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10)
FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3)
REG32(GEM1_REF_CTRL, 0x11c)
FIELD(GEM1_REF_CTRL, CLKACT_RX, 27, 1)
FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1)
FIELD(GEM1_REF_CTRL, CLKACT, 25, 1)
FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10)
FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3)
REG32(GEM_TSU_REF_CTRL, 0x120)
FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1)
FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10)
FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3)
REG32(USB0_BUS_REF_CTRL, 0x124)
FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1)
FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10)
FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3)
REG32(UART0_REF_CTRL, 0x128)
FIELD(UART0_REF_CTRL, CLKACT, 25, 1)
FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10)
FIELD(UART0_REF_CTRL, SRCSEL, 0, 3)
REG32(UART1_REF_CTRL, 0x12c)
FIELD(UART1_REF_CTRL, CLKACT, 25, 1)
FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10)
FIELD(UART1_REF_CTRL, SRCSEL, 0, 3)
REG32(SPI0_REF_CTRL, 0x130)
FIELD(SPI0_REF_CTRL, CLKACT, 25, 1)
FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10)
FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3)
REG32(SPI1_REF_CTRL, 0x134)
FIELD(SPI1_REF_CTRL, CLKACT, 25, 1)
FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10)
FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3)
REG32(CAN0_REF_CTRL, 0x138)
FIELD(CAN0_REF_CTRL, CLKACT, 25, 1)
FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10)
FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3)
REG32(CAN1_REF_CTRL, 0x13c)
FIELD(CAN1_REF_CTRL, CLKACT, 25, 1)
FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10)
FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3)
REG32(I2C0_REF_CTRL, 0x140)
FIELD(I2C0_REF_CTRL, CLKACT, 25, 1)
FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10)
FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3)
REG32(I2C1_REF_CTRL, 0x144)
FIELD(I2C1_REF_CTRL, CLKACT, 25, 1)
FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10)
FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3)
REG32(DBG_LPD_CTRL, 0x148)
FIELD(DBG_LPD_CTRL, CLKACT, 25, 1)
FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10)
FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3)
REG32(TIMESTAMP_REF_CTRL, 0x14c)
FIELD(TIMESTAMP_REF_CTRL, CLKACT, 25, 1)
FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10)
FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3)
REG32(CRL_SAFETY_CHK, 0x150)
REG32(PSM_REF_CTRL, 0x154)
FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10)
FIELD(PSM_REF_CTRL, SRCSEL, 0, 3)
REG32(DBG_TSTMP_CTRL, 0x158)
FIELD(DBG_TSTMP_CTRL, CLKACT, 25, 1)
FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10)
FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
REG32(CPM_TOPSW_REF_CTRL, 0x15c)
FIELD(CPM_TOPSW_REF_CTRL, CLKACT, 25, 1)
FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10)
FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3)
REG32(USB3_DUAL_REF_CTRL, 0x160)
FIELD(USB3_DUAL_REF_CTRL, CLKACT, 25, 1)
FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10)
FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3)
REG32(RST_CPU_R5, 0x300)
FIELD(RST_CPU_R5, RESET_PGE, 4, 1)
FIELD(RST_CPU_R5, RESET_AMBA, 2, 1)
FIELD(RST_CPU_R5, RESET_CPU1, 1, 1)
FIELD(RST_CPU_R5, RESET_CPU0, 0, 1)
REG32(RST_ADMA, 0x304)
FIELD(RST_ADMA, RESET, 0, 1)
REG32(RST_GEM0, 0x308)
FIELD(RST_GEM0, RESET, 0, 1)
REG32(RST_GEM1, 0x30c)
FIELD(RST_GEM1, RESET, 0, 1)
REG32(RST_SPARE, 0x310)
FIELD(RST_SPARE, RESET, 0, 1)
REG32(RST_USB0, 0x314)
FIELD(RST_USB0, RESET, 0, 1)
REG32(RST_UART0, 0x318)
FIELD(RST_UART0, RESET, 0, 1)
REG32(RST_UART1, 0x31c)
FIELD(RST_UART1, RESET, 0, 1)
REG32(RST_SPI0, 0x320)
FIELD(RST_SPI0, RESET, 0, 1)
REG32(RST_SPI1, 0x324)
FIELD(RST_SPI1, RESET, 0, 1)
REG32(RST_CAN0, 0x328)
FIELD(RST_CAN0, RESET, 0, 1)
REG32(RST_CAN1, 0x32c)
FIELD(RST_CAN1, RESET, 0, 1)
REG32(RST_I2C0, 0x330)
FIELD(RST_I2C0, RESET, 0, 1)
REG32(RST_I2C1, 0x334)
FIELD(RST_I2C1, RESET, 0, 1)
REG32(RST_DBG_LPD, 0x338)
FIELD(RST_DBG_LPD, RPU_DBG1_RESET, 5, 1)
FIELD(RST_DBG_LPD, RPU_DBG0_RESET, 4, 1)
FIELD(RST_DBG_LPD, RESET_HSDP, 1, 1)
FIELD(RST_DBG_LPD, RESET, 0, 1)
REG32(RST_GPIO, 0x33c)
FIELD(RST_GPIO, RESET, 0, 1)
REG32(RST_TTC, 0x344)
FIELD(RST_TTC, TTC3_RESET, 3, 1)
FIELD(RST_TTC, TTC2_RESET, 2, 1)
FIELD(RST_TTC, TTC1_RESET, 1, 1)
FIELD(RST_TTC, TTC0_RESET, 0, 1)
REG32(RST_TIMESTAMP, 0x348)
FIELD(RST_TIMESTAMP, RESET, 0, 1)
REG32(RST_SWDT, 0x34c)
FIELD(RST_SWDT, RESET, 0, 1)
REG32(RST_OCM, 0x350)
FIELD(RST_OCM, RESET, 0, 1)
REG32(RST_IPI, 0x354)
FIELD(RST_IPI, RESET, 0, 1)
REG32(RST_SYSMON, 0x358)
FIELD(RST_SYSMON, SEQ_RST, 1, 1)
FIELD(RST_SYSMON, CFG_RST, 0, 1)
REG32(RST_FPD, 0x360)
FIELD(RST_FPD, SRST, 1, 1)
FIELD(RST_FPD, POR, 0, 1)
REG32(PSM_RST_MODE, 0x370)
FIELD(PSM_RST_MODE, WAKEUP, 2, 1)
FIELD(PSM_RST_MODE, RST_MODE, 0, 2)
#define CRL_R_MAX (R_PSM_RST_MODE + 1)
#define RPU_MAX_CPU 2
struct XlnxVersalCRL {
SysBusDevice parent_obj;
qemu_irq irq;
struct {
ARMCPU *cpu_r5[RPU_MAX_CPU];
DeviceState *adma[8];
DeviceState *uart[2];
DeviceState *gem[2];
DeviceState *usb;
} cfg;
RegisterInfoArray *reg_array;
uint32_t regs[CRL_R_MAX];
RegisterInfo regs_info[CRL_R_MAX];
};
#endif

54
include/hw/timer/cadence_ttc.h Normal file
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/*
* Xilinx Zynq cadence TTC model
*
* Copyright (c) 2011 Xilinx Inc.
* Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
* Copyright (c) 2012 PetaLogix Pty Ltd.
* Written By Haibing Ma
* M. Habib
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_TIMER_CADENCE_TTC_H
#define HW_TIMER_CADENCE_TTC_H
#include "hw/sysbus.h"
#include "qemu/timer.h"
typedef struct {
QEMUTimer *timer;
int freq;
uint32_t reg_clock;
uint32_t reg_count;
uint32_t reg_value;
uint16_t reg_interval;
uint16_t reg_match[3];
uint32_t reg_intr;
uint32_t reg_intr_en;
uint32_t reg_event_ctrl;
uint32_t reg_event;
uint64_t cpu_time;
unsigned int cpu_time_valid;
qemu_irq irq;
} CadenceTimerState;
#define TYPE_CADENCE_TTC "cadence_ttc"
OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
struct CadenceTTCState {
SysBusDevice parent_obj;
MemoryRegion iomem;
CadenceTimerState timer[3];
};
#endif