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target/riscv: Use insn_start from DisasContextBase

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To keep the multiple update check, replace insn_start
with insn_start_updated.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-04-06 11:12:14 -10:00
parent e231345027
commit 401aa608d8
1 changed files with 5 additions and 6 deletions
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11
target/riscv/translate.c
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@ -115,8 +115,7 @@ typedef struct DisasContext {
bool itrigger; bool itrigger;
/* FRM is known to contain a valid value. */ /* FRM is known to contain a valid value. */
bool frm_valid; bool frm_valid;
/* TCG of the current insn_start */ bool insn_start_updated;
TCGOp *insn_start;
} DisasContext; } DisasContext;
static inline bool has_ext(DisasContext *ctx, uint32_t ext) static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@ -207,9 +206,9 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
static void decode_save_opc(DisasContext *ctx) static void decode_save_opc(DisasContext *ctx)
{ {
assert(ctx->insn_start != NULL); assert(!ctx->insn_start_updated);
tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); ctx->insn_start_updated = true;
ctx->insn_start = NULL; tcg_set_insn_start_param(ctx->base.insn_start, 1, ctx->opcode);
} }
static void gen_pc_plus_diff(TCGv target, DisasContext *ctx, static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
@ -1224,7 +1223,7 @@ static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
} }
tcg_gen_insn_start(pc_next, 0); tcg_gen_insn_start(pc_next, 0);
ctx->insn_start = tcg_last_op(); ctx->insn_start_updated = false;
} }
static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)