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target-ppc: VSX Stage 4: Add xsaddsp and xssubsp

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This patch adds the VSX Scalar Add Single-Precision (xsaddsp) and
VSX Scalar Subtract Single-Precision (xssubsp) instructions.

The existing VSX_ADD_SUB macro is modified to support the rounding
of the (intermediate) result to single-precision.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Tom Musta 2014-01-15 08:10:33 -06:00 • committed by Alexander Graf
parent e16a626b82
commit 3fd0aadfc1
3 changed files with 22 additions and 7 deletions
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20
target-ppc/fpu_helper.c
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@ -1768,7 +1768,7 @@ static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
* fld - vsr_t field (f32 or f64)
* sfprf - set FPRF
*/
#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf) \
#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) \
void helper_##name(CPUPPCState *env, uint32_t opcode) \
{ \
ppc_vsr_t xt, xa, xb; \
@ -1794,6 +1794,10 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \
} \
} \
\
if (r2sp) { \
xt.fld[i] = helper_frsp(env, xt.fld[i]); \
} \
\
if (sfprf) { \
helper_compute_fprf(env, xt.fld[i], sfprf); \
} \
@ -1802,12 +1806,14 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \
helper_float_check_status(env); \
}
VSX_ADD_SUB(xsadddp, add, 1, float64, f64, 1)
VSX_ADD_SUB(xvadddp, add, 2, float64, f64, 0)
VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0)
VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1)
VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0)
VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0)
VSX_ADD_SUB(xsadddp, add, 1, float64, f64, 1, 0)
VSX_ADD_SUB(xsaddsp, add, 1, float64, f64, 1, 1)
VSX_ADD_SUB(xvadddp, add, 2, float64, f64, 0, 0)
VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0, 0)
VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1, 0)
VSX_ADD_SUB(xssubsp, sub, 1, float64, f64, 1, 1)
VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0, 0)
VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0, 0)
/* VSX_MUL - VSX floating point multiply
* op - instruction mnemonic