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https://github.com/Motorhead1991/qemu.git
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Implement the PXA2xx I2C master controller.
Fix PXA270-specific timers and make minor changes in other PXA parts. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2853 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog
parent
209a4e691d
commit
3f582262e5
8 changed files with 271 additions and 25 deletions
247
hw/pxa2xx.c
247
hw/pxa2xx.c
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@ -69,9 +69,16 @@ static struct {
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#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
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#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
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static uint32_t pxa2xx_i2c_read(void *, target_phys_addr_t);
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static void pxa2xx_i2c_write(void *, target_phys_addr_t, uint32_t);
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static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
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{
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struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
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if (addr > s->pm_base + PCMD31) {
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/* Special case: PWRI2C registers appear in the same range. */
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return pxa2xx_i2c_read(s->i2c[1], addr);
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}
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addr -= s->pm_base;
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switch (addr) {
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@ -92,6 +99,11 @@ static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
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if (addr > s->pm_base + PCMD31) {
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/* Special case: PWRI2C registers appear in the same range. */
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pxa2xx_i2c_write(s->i2c[1], addr, value);
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return;
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}
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addr -= s->pm_base;
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switch (addr) {
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@ -1086,6 +1098,225 @@ static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
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pxa2xx_rtc_write,
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};
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/* I2C Interface */
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struct pxa2xx_i2c_s {
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i2c_slave slave;
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i2c_bus *bus;
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target_phys_addr_t base;
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qemu_irq irq;
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uint16_t control;
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uint16_t status;
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uint8_t ibmr;
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uint8_t data;
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};
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#define IBMR 0x80 /* I2C Bus Monitor register */
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#define IDBR 0x88 /* I2C Data Buffer register */
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#define ICR 0x90 /* I2C Control register */
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#define ISR 0x98 /* I2C Status register */
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#define ISAR 0xa0 /* I2C Slave Address register */
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static void pxa2xx_i2c_update(struct pxa2xx_i2c_s *s)
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{
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uint16_t level = 0;
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level |= s->status & s->control & (1 << 10); /* BED */
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level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
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level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
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level |= s->status & (1 << 9); /* SAD */
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qemu_set_irq(s->irq, !!level);
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}
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/* These are only stubs now. */
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static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
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{
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struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
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switch (event) {
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case I2C_START_SEND:
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s->status |= (1 << 9); /* set SAD */
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s->status &= ~(1 << 0); /* clear RWM */
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break;
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case I2C_START_RECV:
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s->status |= (1 << 9); /* set SAD */
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s->status |= 1 << 0; /* set RWM */
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break;
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case I2C_FINISH:
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s->status |= (1 << 4); /* set SSD */
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break;
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case I2C_NACK:
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s->status |= 1 << 1; /* set ACKNAK */
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break;
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}
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pxa2xx_i2c_update(s);
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}
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static int pxa2xx_i2c_rx(i2c_slave *i2c)
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{
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struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
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if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
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return 0;
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if (s->status & (1 << 0)) { /* RWM */
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s->status |= 1 << 6; /* set ITE */
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}
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pxa2xx_i2c_update(s);
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return s->data;
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}
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static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
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{
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struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
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if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
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return 1;
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if (!(s->status & (1 << 0))) { /* RWM */
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s->status |= 1 << 7; /* set IRF */
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s->data = data;
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}
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pxa2xx_i2c_update(s);
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return 1;
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}
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static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
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{
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struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
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addr -= s->base;
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switch (addr) {
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case ICR:
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return s->control;
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case ISR:
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return s->status | (i2c_bus_busy(s->bus) << 2);
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case ISAR:
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return s->slave.address;
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case IDBR:
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return s->data;
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case IBMR:
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if (s->status & (1 << 2))
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s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
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else
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s->ibmr = 0;
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return s->ibmr;
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default:
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printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
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break;
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}
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return 0;
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}
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static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
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int ack;
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addr -= s->base;
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switch (addr) {
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case ICR:
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s->control = value & 0xfff7;
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if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
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/* TODO: slave mode */
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if (value & (1 << 0)) { /* START condition */
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if (s->data & 1)
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s->status |= 1 << 0; /* set RWM */
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else
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s->status &= ~(1 << 0); /* clear RWM */
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ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
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} else {
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if (s->status & (1 << 0)) { /* RWM */
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s->data = i2c_recv(s->bus);
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if (value & (1 << 2)) /* ACKNAK */
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i2c_nack(s->bus);
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ack = 1;
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} else
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ack = !i2c_send(s->bus, s->data);
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}
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if (value & (1 << 1)) /* STOP condition */
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i2c_end_transfer(s->bus);
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if (ack) {
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if (value & (1 << 0)) /* START condition */
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s->status |= 1 << 6; /* set ITE */
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else
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if (s->status & (1 << 0)) /* RWM */
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s->status |= 1 << 7; /* set IRF */
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else
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s->status |= 1 << 6; /* set ITE */
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s->status &= ~(1 << 1); /* clear ACKNAK */
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} else {
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s->status |= 1 << 6; /* set ITE */
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s->status |= 1 << 10; /* set BED */
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s->status |= 1 << 1; /* set ACKNAK */
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}
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}
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if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
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if (value & (1 << 4)) /* MA */
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i2c_end_transfer(s->bus);
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pxa2xx_i2c_update(s);
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break;
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case ISR:
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s->status &= ~(value & 0x07f0);
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pxa2xx_i2c_update(s);
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break;
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case ISAR:
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i2c_set_slave_address(&s->slave, value & 0x7f);
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break;
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case IDBR:
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s->data = value & 0xff;
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break;
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default:
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printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
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}
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}
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static CPUReadMemoryFunc *pxa2xx_i2c_readfn[] = {
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pxa2xx_i2c_read,
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pxa2xx_i2c_read,
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pxa2xx_i2c_read,
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};
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static CPUWriteMemoryFunc *pxa2xx_i2c_writefn[] = {
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pxa2xx_i2c_write,
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pxa2xx_i2c_write,
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pxa2xx_i2c_write,
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};
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struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
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qemu_irq irq, int ioregister)
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{
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int iomemtype;
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struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *)
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qemu_mallocz(sizeof(struct pxa2xx_i2c_s));
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s->base = base;
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s->irq = irq;
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s->slave.event = pxa2xx_i2c_event;
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s->slave.recv = pxa2xx_i2c_rx;
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s->slave.send = pxa2xx_i2c_tx;
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s->bus = i2c_init_bus();
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if (ioregister) {
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iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
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pxa2xx_i2c_writefn, s);
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cpu_register_physical_memory(s->base & 0xfffff000, 0xfff, iomemtype);
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}
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return s;
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}
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i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s)
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{
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return s->bus;
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}
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/* PXA Inter-IC Sound Controller */
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static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s)
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{
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@ -1544,7 +1775,7 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
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s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
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pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
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s->pic[PXA27X_PIC_OST_4_11], s->env);
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s->pic[PXA27X_PIC_OST_4_11]);
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s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
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@ -1608,6 +1839,12 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
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cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype);
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pxa2xx_rtc_reset(s);
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/* Note that PM registers are in the same page with PWRI2C registers.
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* As a workaround we don't map PWRI2C into memory and we expect
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* PM handlers to call PWRI2C handlers when appropriate. */
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s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 1);
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s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0);
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s->pm_base = 0x40f00000;
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iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
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pxa2xx_pm_writefn, s);
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@ -1643,7 +1880,7 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
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s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
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pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0], s->env);
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pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
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s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
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@ -1707,6 +1944,12 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
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cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype);
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pxa2xx_rtc_reset(s);
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/* Note that PM registers are in the same page with PWRI2C registers.
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* As a workaround we don't map PWRI2C into memory and we expect
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* PM handlers to call PWRI2C handlers when appropriate. */
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s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 1);
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s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0);
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s->pm_base = 0x40f00000;
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iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
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pxa2xx_pm_writefn, s);
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