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target/riscv: Simplify check for Zve32f and Zve64f

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V/Zve64f depend on Zve32f, so we can only check Zve32f in these cases.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-9-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Weiwei Li 2023-02-15 10:05:33 +08:00 • committed by Palmer Dabbelt
parent 51f33081ef
commit 3f4a5a5314
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GPG key ID: 2E1319F35FBB1889
3 changed files with 4 additions and 9 deletions
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8
target/riscv/insn_trans/trans_rvv.c.inc
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@ -173,9 +173,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
{
TCGv s1, dst;
if (!require_rvv(s) ||
!(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
s->cfg_ptr->ext_zve64f)) {
if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
return false;
}
@ -210,9 +208,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
{
TCGv dst;
if (!require_rvv(s) ||
!(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
s->cfg_ptr->ext_zve64f)) {
if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
return false;
}