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hw/riscv: Use the CPU to determine if 32-bit

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Instead of using string compares to determine if a RISC-V machine is
using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids
us having to maintain a list of CPU names to compare against.

This commit also fixes the name of the function to match the
riscv_cpu_is_32bit() function.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 8ab7614e5df93ab5267788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2020-12-16 10:23:08 -08:00
parent 094b072c68
commit 3ed2b8ac2d
5 changed files with 29 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

31
hw/riscv/boot.c
View file

@ -33,28 +33,16 @@
#include <libfdt.h>
bool riscv_is_32_bit(MachineState *machine)
bool riscv_is_32bit(RISCVHartArrayState harts)
{
/*
* To determine if the CPU is 32-bit we need to check a few different CPUs.
*
* If the CPU starts with rv32
* If the CPU is a sifive 3 seriries CPU (E31, U34)
* If it's the Ibex CPU
*/
if (!strncmp(machine->cpu_type, "rv32", 4) ||
(!strncmp(machine->cpu_type, "sifive", 6) &&
machine->cpu_type[8] == '3') ||
!strncmp(machine->cpu_type, "lowrisc-ibex", 12)) {
return true;
} else {
return false;
}
RISCVCPU hart = harts.harts[0];
return riscv_cpu_is_32bit(&hart.env);
}
target_ulong riscv_calc_kernel_start_addr(MachineState *machine,
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts,
target_ulong firmware_end_addr) {
if (riscv_is_32_bit(machine)) {
if (riscv_is_32bit(harts)) {
return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
} else {
return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB);
@ -259,7 +247,8 @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
&address_space_memory);
}
void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr start_addr,
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts,
hwaddr start_addr,
hwaddr rom_base, hwaddr rom_size,
uint64_t kernel_entry,
uint32_t fdt_load_addr, void *fdt)
@ -267,7 +256,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr start_addr,
int i;
uint32_t start_addr_hi32 = 0x00000000;
if (!riscv_is_32_bit(machine)) {
if (!riscv_is_32bit(harts)) {
start_addr_hi32 = start_addr >> 32;
}
/* reset vector */
@ -284,7 +273,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr start_addr,
0x00000000,
/* fw_dyn: */
};
if (riscv_is_32_bit(machine)) {
if (riscv_is_32bit(harts)) {
reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */
reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */
} else {