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A large collection of RISC-V fixes, improvements and features
- Clenaup some left over v1.9 code - Documentation improvements - Support for the shakti_c machine - Internal cleanup of the CSR accesses - Updates to the OpenTitan platform - Support for the virtio-vga - Fix for the saturate subtract in vector extensions - Experimental support for the ePMP spec - A range of other internal code cleanups and bug fixes -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmCaWaYACgkQIeENKd+X cFS97Af/c+Zh5KddhY0qYm6/deabhzn2fPrensOX+UlQbThpbKLHPZ+ceh1GRYBl tqfiQa6ByhLhHk4UihIjJvLL9UW+UUxR3zsUfHcFHGAmy22ms9oiGB+se37gj/YB 2WySYQhHlwW1iz+55mMh+c1wjckFFVjX4dQgh7pl60AJWxNdzNOBUr/BwMZUh0zM UFsYDGS2MF3JId8VkW4Ui4fKTw0HBexK4gKXOsRIpF6R3+PQa3m4ppr/YZfyUy5W o8lZhztoO5TgyGyNpCo6UdG9JlJP5iNnPRTn+ordqJhpNKFTLQeuLBW9gMpB9BiG L1fvPePKz7GWxI/Xrl9uwNyWSYwetA== =6TPt -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210511' into staging A large collection of RISC-V fixes, improvements and features - Clenaup some left over v1.9 code - Documentation improvements - Support for the shakti_c machine - Internal cleanup of the CSR accesses - Updates to the OpenTitan platform - Support for the virtio-vga - Fix for the saturate subtract in vector extensions - Experimental support for the ePMP spec - A range of other internal code cleanups and bug fixes # gpg: Signature made Tue 11 May 2021 11:17:10 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210511: (42 commits) target/riscv: Fix the RV64H decode comment target/riscv: Consolidate RV32/64 16-bit instructions target/riscv: Consolidate RV32/64 32-bit instructions target/riscv: Remove an unused CASE_OP_32_64 macro target/riscv: Remove the unused HSTATUS_WPRI macro target/riscv: Remove the hardcoded SATP_MODE macro target/riscv: Remove the hardcoded MSTATUS_SD macro target/riscv: Remove the hardcoded HGATP_MODE macro target/riscv: Remove the hardcoded SSTATUS_SD macro target/riscv: Remove the hardcoded RVXLEN macro target/riscv: fix a typo with interrupt names fpu/softfloat: set invalid excp flag for RISC-V muladd instructions hw/riscv: Fix OT IBEX reset vector target/riscv: fix exception index on instruction access fault target/riscv: fix vrgather macro index variable type bug target/riscv: Add ePMP support for the Ibex CPU target/riscv/pmp: Remove outdated comment target/riscv: Add a config option for ePMP target/riscv: Implementation of enhanced PMP (ePMP) target/riscv: Add ePMP CSR access functions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
3e9f48bcda
47 changed files with 1760 additions and 790 deletions
74
include/hw/char/shakti_uart.h
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74
include/hw/char/shakti_uart.h
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@ -0,0 +1,74 @@
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/*
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* SHAKTI UART
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*
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* Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_SHAKTI_UART_H
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#define HW_SHAKTI_UART_H
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#include "hw/sysbus.h"
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#include "chardev/char-fe.h"
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#define SHAKTI_UART_BAUD 0x00
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#define SHAKTI_UART_TX 0x04
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#define SHAKTI_UART_RX 0x08
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#define SHAKTI_UART_STATUS 0x0C
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#define SHAKTI_UART_DELAY 0x10
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#define SHAKTI_UART_CONTROL 0x14
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#define SHAKTI_UART_INT_EN 0x18
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#define SHAKTI_UART_IQ_CYCLES 0x1C
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#define SHAKTI_UART_RX_THRES 0x20
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#define SHAKTI_UART_STATUS_TX_EMPTY (1 << 0)
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#define SHAKTI_UART_STATUS_TX_FULL (1 << 1)
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#define SHAKTI_UART_STATUS_RX_NOT_EMPTY (1 << 2)
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#define SHAKTI_UART_STATUS_RX_FULL (1 << 3)
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/* 9600 8N1 is the default setting */
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/* Reg value = (50000000 Hz)/(16 * 9600)*/
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#define SHAKTI_UART_BAUD_DEFAULT 0x0145
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#define SHAKTI_UART_CONTROL_DEFAULT 0x0100
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#define TYPE_SHAKTI_UART "shakti-uart"
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#define SHAKTI_UART(obj) \
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OBJECT_CHECK(ShaktiUartState, (obj), TYPE_SHAKTI_UART)
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typedef struct {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion mmio;
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uint32_t uart_baud;
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uint32_t uart_tx;
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uint32_t uart_rx;
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uint32_t uart_status;
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uint32_t uart_delay;
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uint32_t uart_control;
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uint32_t uart_interrupt;
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uint32_t uart_iq_cycles;
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uint32_t uart_rx_threshold;
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CharBackend chr;
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} ShaktiUartState;
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#endif /* HW_SHAKTI_UART_H */
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@ -82,14 +82,14 @@ enum {
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};
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enum {
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IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
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IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
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IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
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IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
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IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
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IBEX_UART_TX_EMPTY_IRQ = 0x23,
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IBEX_UART_RX_WATERMARK_IRQ = 0x22,
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IBEX_UART_TX_WATERMARK_IRQ = 0x21,
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IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
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IBEX_UART0_RX_TIMEOUT_IRQ = 7,
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IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
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IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
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IBEX_UART0_RX_OVERFLOW_IRQ = 4,
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IBEX_UART0_TX_EMPTY_IRQ = 3,
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IBEX_UART0_RX_WATERMARK_IRQ = 2,
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IBEX_UART0_TX_WATERMARK_IRQ = 1,
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};
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#endif
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75
include/hw/riscv/shakti_c.h
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75
include/hw/riscv/shakti_c.h
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/*
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* Shakti C-class SoC emulation
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*
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* Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_SHAKTI_H
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#define HW_SHAKTI_H
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#include "hw/riscv/riscv_hart.h"
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#include "hw/boards.h"
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#include "hw/char/shakti_uart.h"
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#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
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#define RISCV_SHAKTI_SOC(obj) \
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OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC)
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typedef struct ShaktiCSoCState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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RISCVHartArrayState cpus;
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DeviceState *plic;
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ShaktiUartState uart;
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MemoryRegion rom;
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} ShaktiCSoCState;
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#define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c")
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#define RISCV_SHAKTI_MACHINE(obj) \
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OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE)
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typedef struct ShaktiCMachineState {
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/*< private >*/
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MachineState parent_obj;
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/*< public >*/
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ShaktiCSoCState soc;
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} ShaktiCMachineState;
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enum {
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SHAKTI_C_ROM,
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SHAKTI_C_RAM,
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SHAKTI_C_UART,
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SHAKTI_C_GPIO,
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SHAKTI_C_PLIC,
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SHAKTI_C_CLINT,
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SHAKTI_C_I2C,
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};
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#define SHAKTI_C_PLIC_HART_CONFIG "MS"
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/* Including Interrupt ID 0 (no interrupt)*/
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#define SHAKTI_C_PLIC_NUM_SOURCES 28
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/* Excluding Priority 0 */
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#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
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#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
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#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
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#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
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#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
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#define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000
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#define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000
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#endif
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