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A large collection of RISC-V fixes, improvements and features

Browse source 
- Clenaup some left over v1.9 code
  - Documentation improvements
  - Support for the shakti_c machine
  - Internal cleanup of the CSR accesses
  - Updates to the OpenTitan platform
  - Support for the virtio-vga
  - Fix for the saturate subtract in vector extensions
  - Experimental support for the ePMP spec
  - A range of other internal code cleanups and bug fixes
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210511' into staging

A large collection of RISC-V fixes, improvements and features

 - Clenaup some left over v1.9 code
 - Documentation improvements
 - Support for the shakti_c machine
 - Internal cleanup of the CSR accesses
 - Updates to the OpenTitan platform
 - Support for the virtio-vga
 - Fix for the saturate subtract in vector extensions
 - Experimental support for the ePMP spec
 - A range of other internal code cleanups and bug fixes

# gpg: Signature made Tue 11 May 2021 11:17:10 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210511: (42 commits)
  target/riscv: Fix the RV64H decode comment
  target/riscv: Consolidate RV32/64 16-bit instructions
  target/riscv: Consolidate RV32/64 32-bit instructions
  target/riscv: Remove an unused CASE_OP_32_64 macro
  target/riscv: Remove the unused HSTATUS_WPRI macro
  target/riscv: Remove the hardcoded SATP_MODE macro
  target/riscv: Remove the hardcoded MSTATUS_SD macro
  target/riscv: Remove the hardcoded HGATP_MODE macro
  target/riscv: Remove the hardcoded SSTATUS_SD macro
  target/riscv: Remove the hardcoded RVXLEN macro
  target/riscv: fix a typo with interrupt names
  fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
  hw/riscv: Fix OT IBEX reset vector
  target/riscv: fix exception index on instruction access fault
  target/riscv: fix vrgather macro index variable type bug
  target/riscv: Add ePMP support for the Ibex CPU
  target/riscv/pmp: Remove outdated comment
  target/riscv: Add a config option for ePMP
  target/riscv: Implementation of enhanced PMP (ePMP)
  target/riscv: Add ePMP CSR access functions
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-05-12 17:31:52 +01:00
commit 3e9f48bcda
47 changed files with 1760 additions and 790 deletions
Download patch file Download diff file Expand all files Collapse all files

1
hw/char/meson.build
View file

@ -19,6 +19,7 @@ softmmu_ss.add(when: 'CONFIG_SERIAL', if_true: files('serial.c'))
softmmu_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c'))
softmmu_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c'))
softmmu_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci-multi.c'))
softmmu_ss.add(when: 'CONFIG_SHAKTI', if_true: files('shakti_uart.c'))
softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-console.c'))
softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_console.c'))
softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c'))

185
hw/char/shakti_uart.c Normal file
View file

@ -0,0 +1,185 @@
/*
* SHAKTI UART
*
* Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "hw/char/shakti_uart.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "qemu/log.h"
static uint64_t shakti_uart_read(void *opaque, hwaddr addr, unsigned size)
{
ShaktiUartState *s = opaque;
switch (addr) {
case SHAKTI_UART_BAUD:
return s->uart_baud;
case SHAKTI_UART_RX:
qemu_chr_fe_accept_input(&s->chr);
s->uart_status &= ~SHAKTI_UART_STATUS_RX_NOT_EMPTY;
return s->uart_rx;
case SHAKTI_UART_STATUS:
return s->uart_status;
case SHAKTI_UART_DELAY:
return s->uart_delay;
case SHAKTI_UART_CONTROL:
return s->uart_control;
case SHAKTI_UART_INT_EN:
return s->uart_interrupt;
case SHAKTI_UART_IQ_CYCLES:
return s->uart_iq_cycles;
case SHAKTI_UART_RX_THRES:
return s->uart_rx_threshold;
default:
/* Also handles TX REG which is write only */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
}
return 0;
}
static void shakti_uart_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
ShaktiUartState *s = opaque;
uint32_t value = data;
uint8_t ch;
switch (addr) {
case SHAKTI_UART_BAUD:
s->uart_baud = value;
break;
case SHAKTI_UART_TX:
ch = value;
qemu_chr_fe_write_all(&s->chr, &ch, 1);
s->uart_status &= ~SHAKTI_UART_STATUS_TX_FULL;
break;
case SHAKTI_UART_STATUS:
s->uart_status = value;
break;
case SHAKTI_UART_DELAY:
s->uart_delay = value;
break;
case SHAKTI_UART_CONTROL:
s->uart_control = value;
break;
case SHAKTI_UART_INT_EN:
s->uart_interrupt = value;
break;
case SHAKTI_UART_IQ_CYCLES:
s->uart_iq_cycles = value;
break;
case SHAKTI_UART_RX_THRES:
s->uart_rx_threshold = value;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
}
}
static const MemoryRegionOps shakti_uart_ops = {
.read = shakti_uart_read,
.write = shakti_uart_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {.min_access_size = 1, .max_access_size = 4},
.valid = {.min_access_size = 1, .max_access_size = 4},
};
static void shakti_uart_reset(DeviceState *dev)
{
ShaktiUartState *s = SHAKTI_UART(dev);
s->uart_baud = SHAKTI_UART_BAUD_DEFAULT;
s->uart_tx = 0x0;
s->uart_rx = 0x0;
s->uart_status = 0x0000;
s->uart_delay = 0x0000;
s->uart_control = SHAKTI_UART_CONTROL_DEFAULT;
s->uart_interrupt = 0x0000;
s->uart_iq_cycles = 0x00;
s->uart_rx_threshold = 0x00;
}
static int shakti_uart_can_receive(void *opaque)
{
ShaktiUartState *s = opaque;
return !(s->uart_status & SHAKTI_UART_STATUS_RX_NOT_EMPTY);
}
static void shakti_uart_receive(void *opaque, const uint8_t *buf, int size)
{
ShaktiUartState *s = opaque;
s->uart_rx = *buf;
s->uart_status |= SHAKTI_UART_STATUS_RX_NOT_EMPTY;
}
static void shakti_uart_realize(DeviceState *dev, Error **errp)
{
ShaktiUartState *sus = SHAKTI_UART(dev);
qemu_chr_fe_set_handlers(&sus->chr, shakti_uart_can_receive,
shakti_uart_receive, NULL, NULL, sus, NULL, true);
}
static void shakti_uart_instance_init(Object *obj)
{
ShaktiUartState *sus = SHAKTI_UART(obj);
memory_region_init_io(&sus->mmio,
obj,
&shakti_uart_ops,
sus,
TYPE_SHAKTI_UART,
0x1000);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &sus->mmio);
}
static Property shakti_uart_properties[] = {
DEFINE_PROP_CHR("chardev", ShaktiUartState, chr),
DEFINE_PROP_END_OF_LIST(),
};
static void shakti_uart_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = shakti_uart_reset;
dc->realize = shakti_uart_realize;
device_class_set_props(dc, shakti_uart_properties);
}
static const TypeInfo shakti_uart_info = {
.name = TYPE_SHAKTI_UART,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ShaktiUartState),
.class_init = shakti_uart_class_init,
.instance_init = shakti_uart_instance_init,
};
static void shakti_uart_register_types(void)
{
type_register_static(&shakti_uart_info);
}
type_init(shakti_uart_register_types)

4
hw/char/trace-events
View file

@ -90,6 +90,10 @@ cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"
nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
# shakti_uart.c
shakti_uart_read(uint64_t addr, uint16_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx16 " size %u"
shakti_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
# exynos4210_uart.c
exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)"
exynos_uart_dmaready(uint32_t channel) "UART%d: DMA ready"

20
hw/intc/ibex_plic.c
View file

@ -225,23 +225,23 @@ static void ibex_plic_irq_request(void *opaque, int irq, int level)
static Property ibex_plic_properties[] = {
DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80),
DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3),
DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c),
DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3),
DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18),
DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80),
DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200),
DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3),
DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x20c),
DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210),
DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
DEFINE_PROP_END_OF_LIST(),
};

11
hw/riscv/Kconfig
View file

@ -19,9 +19,20 @@ config OPENTITAN
select IBEX
select UNIMP
config SHAKTI
bool
config SHAKTI_C
bool
select UNIMP
select SHAKTI
select SIFIVE_CLINT
select SIFIVE_PLIC
config RISCV_VIRT
bool
imply PCI_DEVICES
imply VIRTIO_VGA
imply TEST_DEVICES
select GOLDFISH_RTC
select MSI_NONBROKEN

1
hw/riscv/meson.build
View file

@ -4,6 +4,7 @@ riscv_ss.add(files('numa.c'))
riscv_ss.add(files('riscv_hart.c'))
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))

10
hw/riscv/opentitan.c
View file

@ -119,7 +119,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
&error_abort);
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
/* Boot ROM */
@ -148,16 +148,16 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
0, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_UART_TX_WATERMARK_IRQ));
IBEX_UART0_TX_WATERMARK_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
1, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_UART_RX_WATERMARK_IRQ));
IBEX_UART0_RX_WATERMARK_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
2, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_UART_TX_EMPTY_IRQ));
IBEX_UART0_TX_EMPTY_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
3, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_UART_RX_OVERFLOW_IRQ));
IBEX_UART0_RX_OVERFLOW_IRQ));
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);

181
hw/riscv/shakti_c.c Normal file
View file

@ -0,0 +1,181 @@
/*
* Shakti C-class SoC emulation
*
* Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "hw/boards.h"
#include "hw/riscv/shakti_c.h"
#include "qapi/error.h"
#include "hw/intc/sifive_plic.h"
#include "hw/intc/sifive_clint.h"
#include "sysemu/sysemu.h"
#include "hw/qdev-properties.h"
#include "exec/address-spaces.h"
#include "hw/riscv/boot.h"
static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} shakti_c_memmap[] = {
[SHAKTI_C_ROM] = { 0x00001000, 0x2000 },
[SHAKTI_C_RAM] = { 0x80000000, 0x0 },
[SHAKTI_C_UART] = { 0x00011300, 0x00040 },
[SHAKTI_C_GPIO] = { 0x020d0000, 0x00100 },
[SHAKTI_C_PLIC] = { 0x0c000000, 0x20000 },
[SHAKTI_C_CLINT] = { 0x02000000, 0xc0000 },
[SHAKTI_C_I2C] = { 0x20c00000, 0x00100 },
};
static void shakti_c_machine_state_init(MachineState *mstate)
{
ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
/* Allow only Shakti C CPU for this platform */
if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
error_report("This board can only be used with Shakti C CPU");
exit(1);
}
/* Initialize SoC */
object_initialize_child(OBJECT(mstate), "soc", &sms->soc,
TYPE_RISCV_SHAKTI_SOC);
qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
/* register RAM */
memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
mstate->ram_size, &error_fatal);
memory_region_add_subregion(system_memory,
shakti_c_memmap[SHAKTI_C_RAM].base,
main_mem);
/* ROM reset vector */
riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
shakti_c_memmap[SHAKTI_C_RAM].base,
shakti_c_memmap[SHAKTI_C_ROM].base,
shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0,
NULL);
if (mstate->firmware) {
riscv_load_firmware(mstate->firmware,
shakti_c_memmap[SHAKTI_C_RAM].base,
NULL);
}
}
static void shakti_c_machine_instance_init(Object *obj)
{
}
static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
{
MachineClass *mc = MACHINE_CLASS(klass);
mc->desc = "RISC-V Board compatible with Shakti SDK";
mc->init = shakti_c_machine_state_init;
mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
}
static const TypeInfo shakti_c_machine_type_info = {
.name = TYPE_RISCV_SHAKTI_MACHINE,
.parent = TYPE_MACHINE,
.class_init = shakti_c_machine_class_init,
.instance_init = shakti_c_machine_instance_init,
.instance_size = sizeof(ShaktiCMachineState),
};
static void shakti_c_machine_type_info_register(void)
{
type_register_static(&shakti_c_machine_type_info);
}
type_init(shakti_c_machine_type_info_register)
static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
{
ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
MemoryRegion *system_memory = get_system_memory();
sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
(char *)SHAKTI_C_PLIC_HART_CONFIG, 0,
SHAKTI_C_PLIC_NUM_SOURCES,
SHAKTI_C_PLIC_NUM_PRIORITIES,
SHAKTI_C_PLIC_PRIORITY_BASE,
SHAKTI_C_PLIC_PENDING_BASE,
SHAKTI_C_PLIC_ENABLE_BASE,
SHAKTI_C_PLIC_ENABLE_STRIDE,
SHAKTI_C_PLIC_CONTEXT_BASE,
SHAKTI_C_PLIC_CONTEXT_STRIDE,
shakti_c_memmap[SHAKTI_C_PLIC].size);
sifive_clint_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
SIFIVE_CLINT_TIMEBASE_FREQ, false);
qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0));
if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0,
shakti_c_memmap[SHAKTI_C_UART].base);
/* ROM */
memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
memory_region_add_subregion(system_memory,
shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom);
}
static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = shakti_c_soc_state_realize;
}
static void shakti_c_soc_instance_init(Object *obj)
{
ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART);
/*
* CPU type is fixed and we are not supporting passing from commandline yet.
* So let it be in instance_init. When supported should use ms->cpu_type
* instead of TYPE_RISCV_CPU_SHAKTI_C
*/
object_property_set_str(OBJECT(&sss->cpus), "cpu-type",
TYPE_RISCV_CPU_SHAKTI_C, &error_abort);
object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1,
&error_abort);
}
static const TypeInfo shakti_c_type_info = {
.name = TYPE_RISCV_SHAKTI_SOC,
.parent = TYPE_DEVICE,
.class_init = shakti_c_soc_class_init,
.instance_init = shakti_c_soc_instance_init,
.instance_size = sizeof(ShaktiCSoCState),
};
static void shakti_c_type_info_register(void)
{
type_register_static(&shakti_c_type_info);
}
type_init(shakti_c_type_info_register)

2
hw/riscv/sifive_e.c
View file

@ -48,7 +48,7 @@
#include "sysemu/arch_init.h"
#include "sysemu/sysemu.h"
static MemMapEntry sifive_e_memmap[] = {
static const MemMapEntry sifive_e_memmap[] = {
[SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
[SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
[SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },