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qdev: Convert uses of qdev_create() with Coccinelle

Browse source 
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion.  More to come in
this series.

Coccinelle script:

    @ depends on !(file in "hw/arm/highbank.c")@
    expression bus, type_name, dev, expr;
    @@
    -    dev = qdev_create(bus, type_name);
    +    dev = qdev_new(type_name);
         ... when != dev = expr
    -    qdev_init_nofail(dev);
    +    qdev_realize_and_unref(dev, bus, &error_fatal);

    @@
    expression bus, type_name, dev, expr;
    identifier DOWN;
    @@
    -    dev = DOWN(qdev_create(bus, type_name));
    +    dev = DOWN(qdev_new(type_name));
         ... when != dev = expr
    -    qdev_init_nofail(DEVICE(dev));
    +    qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);

    @@
    expression bus, type_name, expr;
    identifier dev;
    @@
    -    DeviceState *dev = qdev_create(bus, type_name);
    +    DeviceState *dev = qdev_new(type_name);
         ... when != dev = expr
    -    qdev_init_nofail(dev);
    +    qdev_realize_and_unref(dev, bus, &error_fatal);

    @@
    expression bus, type_name, dev, expr, errp;
    symbol true;
    @@
    -    dev = qdev_create(bus, type_name);
    +    dev = qdev_new(type_name);
         ... when != dev = expr
    -    object_property_set_bool(OBJECT(dev), true, "realized", errp);
    +    qdev_realize_and_unref(dev, bus, errp);

    @@
    expression bus, type_name, expr, errp;
    identifier dev;
    symbol true;
    @@
    -    DeviceState *dev = qdev_create(bus, type_name);
    +    DeviceState *dev = qdev_new(type_name);
         ... when != dev = expr
    -    object_property_set_bool(OBJECT(dev), true, "realized", errp);
    +    qdev_realize_and_unref(dev, bus, errp);

The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name.  Covered by the
next commit's manual conversions.

Missing #include "qapi/error.h" added manually.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
This commit is contained in:
Markus Armbruster 2020-06-10 07:31:58 +02:00
parent dc3edf8d8a
commit 3e80f6902c
127 changed files with 581 additions and 552 deletions
Download patch file Download diff file Expand all files Collapse all files

7
hw/arm/aspeed.c
View file

@ -241,13 +241,14 @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
{
DeviceState *card;
card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
TYPE_SD_CARD);
card = qdev_new(TYPE_SD_CARD);
if (dinfo) {
qdev_prop_set_drive(card, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
qdev_realize_and_unref(card,
qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
&error_fatal);
}
static void aspeed_machine_init(MachineState *machine)

4
hw/arm/cubieboard.c
View file

@ -92,9 +92,9 @@ static void cubieboard_init(MachineState *machine)
bus = qdev_get_child_bus(DEVICE(a10), "sd-bus");
/* Plug in SD card */
carddev = qdev_create(bus, TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
qdev_realize_and_unref(carddev, bus, &error_fatal);
memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
machine->ram);

41
hw/arm/exynos4210.c
View file

@ -173,7 +173,7 @@ static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate,
DeviceState *dev;
int i;
dev = qdev_create(NULL, "pl330");
dev = qdev_new("pl330");
qdev_prop_set_uint8(dev, "num_events", nevents);
qdev_prop_set_uint8(dev, "num_chnls", 8);
qdev_prop_set_uint8(dev, "num_periph_req", nreq);
@ -184,7 +184,7 @@ static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate,
qdev_prop_set_uint8(dev, "rd_q_dep", 8);
qdev_prop_set_uint8(dev, "data_width", width);
qdev_prop_set_uint16(dev, "data_buffer_dep", width);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, base);
@ -232,9 +232,9 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
/* IRQ Gate */
for (i = 0; i < EXYNOS4210_NCPUS; i++) {
dev = qdev_create(NULL, "exynos4210.irq_gate");
dev = qdev_new("exynos4210.irq_gate");
qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
/* Get IRQ Gate input in gate_irq */
for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
gate_irq[i][n] = qdev_get_gpio_in(dev, n);
@ -247,9 +247,9 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
}
/* Private memory region and Internal GIC */
dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
dev = qdev_new(TYPE_A9MPCORE_PRIV);
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
@ -263,9 +263,9 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
/* External GIC */
dev = qdev_create(NULL, "exynos4210.gic");
dev = qdev_new("exynos4210.gic");
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
/* Map CPU interface */
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
@ -279,8 +279,8 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
}
/* Internal Interrupt Combiner */
dev = qdev_create(NULL, "exynos4210.combiner");
qdev_init_nofail(dev);
dev = qdev_new("exynos4210.combiner");
qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
@ -289,9 +289,9 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
/* External Interrupt Combiner */
dev = qdev_create(NULL, "exynos4210.combiner");
dev = qdev_new("exynos4210.combiner");
qdev_prop_set_uint32(dev, "external", 1);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
@ -353,8 +353,8 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
NULL);
/* Multi Core Timer */
dev = qdev_create(NULL, "exynos4210.mct");
qdev_init_nofail(dev);
dev = qdev_new("exynos4210.mct");
qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
for (n = 0; n < 4; n++) {
/* Connect global timer interrupts to Combiner gpio_in */
@ -379,8 +379,8 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
}
dev = qdev_create(NULL, "exynos4210.i2c");
qdev_init_nofail(dev);
dev = qdev_new("exynos4210.i2c");
qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
sysbus_connect_irq(busdev, 0, i2c_irq);
sysbus_mmio_map(busdev, 0, addr);
@ -423,9 +423,9 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
* public datasheet which is very similar (implementing
* MMC Specification Version 4.0 being the only difference noted)
*/
dev = qdev_create(NULL, TYPE_S3C_SDHCI);
dev = qdev_new(TYPE_S3C_SDHCI);
qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n));
@ -433,9 +433,10 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
di = drive_get(IF_SD, 0, n);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_abort);
qdev_init_nofail(carddev);
qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
&error_fatal);
}
/*** Display controller (FIMD) ***/

4
hw/arm/exynos4_boards.c
View file

@ -81,10 +81,10 @@ static void lan9215_init(uint32_t base, qemu_irq irq)
/* This should be a 9215 but the 9118 is close enough */
if (nd_table[0].used) {
qemu_check_nic_model(&nd_table[0], "lan9118");
dev = qdev_create(NULL, TYPE_LAN9118);
dev = qdev_new(TYPE_LAN9118);
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_prop_set_uint32(dev, "mode_16bit", 1);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);

5
hw/arm/imx25_pdk.c
View file

@ -130,10 +130,9 @@ static void imx25_pdk_init(MachineState *machine)
di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
bus = qdev_get_child_bus(DEVICE(&s->soc.esdhc[i]), "sd-bus");
carddev = qdev_create(bus, TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true,
"realized", &error_fatal);
qdev_realize_and_unref(carddev, bus, &error_fatal);
}
/*

4
hw/arm/integratorcp.c
View file

@ -620,9 +620,9 @@ static void integratorcp_init(MachineState *machine)
0, ram_size);
memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
dev = qdev_create(NULL, TYPE_INTEGRATOR_CM);
dev = qdev_new(TYPE_INTEGRATOR_CM);
qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,

5
hw/arm/mcimx6ul-evk.c
View file

@ -54,10 +54,9 @@ static void mcimx6ul_evk_init(MachineState *machine)
di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus");
carddev = qdev_create(bus, TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true,
"realized", &error_fatal);
qdev_realize_and_unref(carddev, bus, &error_fatal);
}
if (!qtest_enabled()) {

5
hw/arm/mcimx7d-sabre.c
View file

@ -56,10 +56,9 @@ static void mcimx7d_sabre_init(MachineState *machine)
di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus");
carddev = qdev_create(bus, TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true,
"realized", &error_fatal);
qdev_realize_and_unref(carddev, bus, &error_fatal);
}
if (!qtest_enabled()) {

4
hw/arm/mps2-tz.c
View file

@ -246,9 +246,9 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
* except that it doesn't support the checksum-offload feature.
*/
qemu_check_nic_model(nd, "lan9118");
mms->lan9118 = qdev_create(NULL, TYPE_LAN9118);
mms->lan9118 = qdev_new(TYPE_LAN9118);
qdev_set_nic_properties(mms->lan9118, nd);
qdev_init_nofail(mms->lan9118);
qdev_realize_and_unref(mms->lan9118, NULL, &error_fatal);
s = SYS_BUS_DEVICE(mms->lan9118);
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16));

4
hw/arm/msf2-som.c
View file

@ -61,7 +61,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
&error_fatal);
memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
dev = qdev_create(NULL, TYPE_MSF2_SOC);
dev = qdev_new(TYPE_MSF2_SOC);
qdev_prop_set_string(dev, "part-name", "M2S010");
qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type);
@ -77,7 +77,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
qdev_prop_set_uint32(dev, "apb0div", 2);
qdev_prop_set_uint32(dev, "apb1div", 2);
object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
qdev_realize_and_unref(dev, NULL, &error_fatal);
soc = MSF2_SOC(dev);

8
hw/arm/musicpal.c
View file

@ -1651,9 +1651,9 @@ static void musicpal_init(MachineState *machine)
sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL);
qemu_check_nic_model(&nd_table[0], "mv88w8618");
dev = qdev_create(NULL, TYPE_MV88W8618_ETH);
dev = qdev_new(TYPE_MV88W8618_ETH);
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
@ -1688,11 +1688,11 @@ static void musicpal_init(MachineState *machine)
}
wm8750_dev = i2c_create_slave(i2c, TYPE_WM8750, MP_WM_ADDR);
dev = qdev_create(NULL, TYPE_MV88W8618_AUDIO);
dev = qdev_new(TYPE_MV88W8618_AUDIO);
s = SYS_BUS_DEVICE(dev);
object_property_set_link(OBJECT(dev), OBJECT(wm8750_dev),
"wm8750", NULL);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);

4
hw/arm/netduino2.c
View file

@ -34,9 +34,9 @@ static void netduino2_init(MachineState *machine)
{
DeviceState *dev;
dev = qdev_create(NULL, TYPE_STM32F205_SOC);
dev = qdev_new(TYPE_STM32F205_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
qdev_realize_and_unref(dev, NULL, &error_fatal);
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
FLASH_SIZE);

4
hw/arm/netduinoplus2.c
View file

@ -34,9 +34,9 @@ static void netduinoplus2_init(MachineState *machine)
{
DeviceState *dev;
dev = qdev_create(NULL, TYPE_STM32F405_SOC);
dev = qdev_new(TYPE_STM32F405_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
qdev_realize_and_unref(dev, NULL, &error_fatal);
armv7m_load_kernel(ARM_CPU(first_cpu),
machine->kernel_filename,

8
hw/arm/nseries.c
View file

@ -174,7 +174,7 @@ static void n8x0_nand_setup(struct n800_s *s)
char *otp_region;
DriveInfo *dinfo;
s->nand = qdev_create(NULL, "onenand");
s->nand = qdev_new("onenand");
qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
/* Either 0x40 or 0x48 are OK for the device ID */
qdev_prop_set_uint16(s->nand, "device_id", 0x48);
@ -185,7 +185,7 @@ static void n8x0_nand_setup(struct n800_s *s)
qdev_prop_set_drive(s->nand, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
qdev_init_nofail(s->nand);
qdev_realize_and_unref(s->nand, NULL, &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0,
qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO));
omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS,
@ -802,9 +802,9 @@ static void n8x0_uart_setup(struct n800_s *s)
static void n8x0_usb_setup(struct n800_s *s)
{
SysBusDevice *dev;
s->usb = qdev_create(NULL, "tusb6010");
s->usb = qdev_new("tusb6010");
dev = SYS_BUS_DEVICE(s->usb);
qdev_init_nofail(s->usb);
qdev_realize_and_unref(s->usb, NULL, &error_fatal);
sysbus_connect_irq(dev, 0,
qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO));
/* Using the NOR interface */

16
hw/arm/omap1.c
View file

@ -3887,20 +3887,20 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
s->ih[0] = qdev_create(NULL, "omap-intc");
s->ih[0] = qdev_new("omap-intc");
qdev_prop_set_uint32(s->ih[0], "size", 0x100);
omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "arminth_ck"));
qdev_init_nofail(s->ih[0]);
qdev_realize_and_unref(s->ih[0], NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(s->ih[0]);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
sysbus_connect_irq(busdev, 1,
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
sysbus_mmio_map(busdev, 0, 0xfffecb00);
s->ih[1] = qdev_create(NULL, "omap-intc");
s->ih[1] = qdev_new("omap-intc");
qdev_prop_set_uint32(s->ih[1], "size", 0x800);
omap_intc_set_iclk(OMAP_INTC(s->ih[1]), omap_findclk(s, "arminth_ck"));
qdev_init_nofail(s->ih[1]);
qdev_realize_and_unref(s->ih[1], NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(s->ih[1]);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ));
@ -4010,10 +4010,10 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO),
s->wakeup, omap_findclk(s, "clk32-kHz"));
s->gpio = qdev_create(NULL, "omap-gpio");
s->gpio = qdev_new("omap-gpio");
qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck"));
qdev_init_nofail(s->gpio);
qdev_realize_and_unref(s->gpio, NULL, &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1));
sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000);
@ -4028,10 +4028,10 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
s->pwt = omap_pwt_init(system_memory, 0xfffb6000,
omap_findclk(s, "armxor_ck"));
s->i2c[0] = qdev_create(NULL, "omap_i2c");
s->i2c[0] = qdev_new("omap_i2c");
qdev_prop_set_uint8(s->i2c[0], "revision", 0x11);
omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "mpuper_ck"));
qdev_init_nofail(s->i2c[0]);
qdev_realize_and_unref(s->i2c[0], NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(s->i2c[0]);
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C));
sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]);

16
hw/arm/omap2.c
View file

@ -2306,11 +2306,11 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54);
/* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
s->ih[0] = qdev_create(NULL, "omap2-intc");
s->ih[0] = qdev_new("omap2-intc");
qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
omap_intc_set_fclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_fclk"));
omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_iclk"));
qdev_init_nofail(s->ih[0]);
qdev_realize_and_unref(s->ih[0], NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(s->ih[0]);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
@ -2423,11 +2423,11 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
omap_findclk(s, "clk32-kHz"),
omap_findclk(s, "core_l4_iclk"));
s->i2c[0] = qdev_create(NULL, "omap_i2c");
s->i2c[0] = qdev_new("omap_i2c");
qdev_prop_set_uint8(s->i2c[0], "revision", 0x34);
omap_i2c_set_iclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.iclk"));
omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.fclk"));
qdev_init_nofail(s->i2c[0]);
qdev_realize_and_unref(s->i2c[0], NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(s->i2c[0]);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ));
@ -2435,11 +2435,11 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C1_RX]);
sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 5), 0));
s->i2c[1] = qdev_create(NULL, "omap_i2c");
s->i2c[1] = qdev_new("omap_i2c");
qdev_prop_set_uint8(s->i2c[1], "revision", 0x34);
omap_i2c_set_iclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.iclk"));
omap_i2c_set_fclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.fclk"));
qdev_init_nofail(s->i2c[1]);
qdev_realize_and_unref(s->i2c[1], NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(s->i2c[1]);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ));
@ -2447,7 +2447,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C2_RX]);
sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 6), 0));
s->gpio = qdev_create(NULL, "omap2-gpio");
s->gpio = qdev_new("omap2-gpio");
qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
omap2_gpio_set_iclk(OMAP2_GPIO(s->gpio), omap_findclk(s, "gpio_iclk"));
omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 0, omap_findclk(s, "gpio1_dbclk"));
@ -2458,7 +2458,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 4,
omap_findclk(s, "gpio5_dbclk"));
}
qdev_init_nofail(s->gpio);
qdev_realize_and_unref(s->gpio, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(s->gpio);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1));

4
hw/arm/orangepi.c
View file

@ -94,9 +94,9 @@ static void orangepi_init(MachineState *machine)
bus = qdev_get_child_bus(DEVICE(h3), "sd-bus");
/* Plug in SD card */
carddev = qdev_create(bus, TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
qdev_realize_and_unref(carddev, bus, &error_fatal);
/* SDRAM */
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],

8
hw/arm/pxa2xx.c
View file

@ -1510,10 +1510,10 @@ PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
PXA2xxI2CState *s;
I2CBus *i2cbus;
dev = qdev_create(NULL, TYPE_PXA2XX_I2C);
dev = qdev_new(TYPE_PXA2XX_I2C);
qdev_prop_set_uint32(dev, "size", region_size + 1);
qdev_prop_set_uint32(dev, "offset", base & region_size);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
i2c_dev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
@ -2073,9 +2073,9 @@ static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
DeviceState *dev;
SysBusDevice *sbd;
dev = qdev_create(NULL, TYPE_PXA2XX_FIR);
dev = qdev_new(TYPE_PXA2XX_FIR);
qdev_prop_set_chr(dev, "chardev", chr);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sbd = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sbd, 0, base);
sysbus_connect_irq(sbd, 0, irq);

5
hw/arm/pxa2xx_gpio.c
View file

@ -14,6 +14,7 @@
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/pxa.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
@ -269,10 +270,10 @@ DeviceState *pxa2xx_gpio_init(hwaddr base,
CPUState *cs = CPU(cpu);
DeviceState *dev;
dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
dev = qdev_new(TYPE_PXA2XX_GPIO);
qdev_prop_set_int32(dev, "lines", lines);
qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,

5
hw/arm/pxa2xx_pic.c
View file

@ -9,6 +9,7 @@
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "cpu.h"
#include "hw/arm/pxa.h"
@ -267,7 +268,7 @@ static int pxa2xx_pic_post_load(void *opaque, int version_id)
DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
{
DeviceState *dev = qdev_create(NULL, TYPE_PXA2XX_PIC);
DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC);
PXA2xxPICState *s = PXA2XX_PIC(dev);
s->cpu = cpu;
@ -279,7 +280,7 @@ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
s->is_fiq[0] = 0;
s->is_fiq[1] = 0;
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);

4
hw/arm/raspi.c
View file

@ -297,9 +297,9 @@ static void raspi_machine_init(MachineState *machine)
error_report("No SD bus found in SOC object");
exit(1);
}
carddev = qdev_create(bus, TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
qdev_realize_and_unref(carddev, bus, &error_fatal);
vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size",
&error_abort);

20
hw/arm/realview.c
View file

@ -161,16 +161,16 @@ static void realview_init(MachineState *machine,
}
sys_id = is_pb ? 0x01780500 : 0xc1400400;
sysctl = qdev_create(NULL, "realview_sysctl");
sysctl = qdev_new("realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
qdev_init_nofail(sysctl);
qdev_realize_and_unref(sysctl, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
if (is_mpcore) {
dev = qdev_create(NULL, is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore");
dev = qdev_new(is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore");
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, periphbase);
for (n = 0; n < smp_cpus; n++) {
@ -188,9 +188,9 @@ static void realview_init(MachineState *machine,
pic[n] = qdev_get_gpio_in(dev, n);
}
pl041 = qdev_create(NULL, "pl041");
pl041 = qdev_new("pl041");
qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
qdev_init_nofail(pl041);
qdev_realize_and_unref(pl041, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]);
@ -203,10 +203,10 @@ static void realview_init(MachineState *machine,
pl011_create(0x1000c000, pic[15], serial_hd(3));
/* DMA controller is optional, apparently. */
dev = qdev_create(NULL, "pl081");
dev = qdev_new("pl081");
object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream",
&error_fatal);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, 0x10030000);
sysbus_connect_irq(busdev, 0, pic[24]);
@ -239,9 +239,9 @@ static void realview_init(MachineState *machine,
sysbus_create_simple("pl031", 0x10017000, pic[10]);
if (!is_pb) {
dev = qdev_create(NULL, "realview_pci");
dev = qdev_new("realview_pci");
busdev = SYS_BUS_DEVICE(dev);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */
sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */
sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */

20
hw/arm/sbsa-ref.c
View file

@ -339,7 +339,7 @@ static void create_gic(SBSAMachineState *sms)
gictype = gicv3_class_name();
sms->gic = qdev_create(NULL, gictype);
sms->gic = qdev_new(gictype);
qdev_prop_set_uint32(sms->gic, "revision", 3);
qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus);
/*
@ -356,7 +356,7 @@ static void create_gic(SBSAMachineState *sms)
qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
qdev_init_nofail(sms->gic);
qdev_realize_and_unref(sms->gic, NULL, &error_fatal);
gicbusdev = SYS_BUS_DEVICE(sms->gic);
sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base);
@ -409,11 +409,11 @@ static void create_uart(const SBSAMachineState *sms, int uart,
{
hwaddr base = sbsa_ref_memmap[uart].base;
int irq = sbsa_ref_irqmap[uart];
DeviceState *dev = qdev_create(NULL, TYPE_PL011);
DeviceState *dev = qdev_new(TYPE_PL011);
SysBusDevice *s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
memory_region_add_subregion(mem, base,
sysbus_mmio_get_region(s, 0));
sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
@ -464,9 +464,9 @@ static void create_ahci(const SBSAMachineState *sms)
AHCIState *ahci;
int i;
dev = qdev_create(NULL, "sysbus-ahci");
dev = qdev_new("sysbus-ahci");
qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
@ -497,11 +497,11 @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
DeviceState *dev;
int i;
dev = qdev_create(NULL, "arm-smmuv3");
dev = qdev_new("arm-smmuv3");
object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
&error_abort);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < NUM_SMMU_IRQS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
@ -525,8 +525,8 @@ static void create_pcie(SBSAMachineState *sms)
PCIHostState *pci;
int i;
dev = qdev_create(NULL, TYPE_GPEX_HOST);
qdev_init_nofail(dev);
dev = qdev_new(TYPE_GPEX_HOST);
qdev_realize_and_unref(dev, NULL, &error_fatal);
/* Map ECAM space */
ecam_alias = g_new0(MemoryRegion, 1);

4
hw/arm/spitz.c
View file

@ -155,7 +155,7 @@ static void sl_flash_register(PXA2xxState *cpu, int size)
{
DeviceState *dev;
dev = qdev_create(NULL, TYPE_SL_NAND);
dev = qdev_new(TYPE_SL_NAND);
qdev_prop_set_uint8(dev, "manf_id", NAND_MFR_SAMSUNG);
if (size == FLASH_128M)
@ -163,7 +163,7 @@ static void sl_flash_register(PXA2xxState *cpu, int size)
else if (size == FLASH_1024M)
qdev_prop_set_uint8(dev, "chip_id", 0xf1);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, FLASH_BASE);
}

12
hw/arm/stellaris.c
View file

@ -1308,14 +1308,14 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
&error_fatal);
memory_region_add_subregion(system_memory, 0x20000000, sram);
nvic = qdev_create(NULL, TYPE_ARMV7M);
nvic = qdev_new(TYPE_ARMV7M);
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
qdev_prop_set_bit(nvic, "enable-bitband", true);
object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()),
"memory", &error_abort);
/* This will exit with an error if the user passed us a bad cpu_type */
qdev_init_nofail(nvic);
qdev_realize_and_unref(nvic, NULL, &error_fatal);
qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
qemu_allocate_irq(&do_sys_reset, NULL, 0));
@ -1347,13 +1347,13 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
if (board->dc1 & (1 << 3)) { /* watchdog present */
dev = qdev_create(NULL, TYPE_LUMINARY_WATCHDOG);
dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
/* system_clock_scale is valid now */
uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;
qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev),
0,
0x40000000u);
@ -1425,9 +1425,9 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
qemu_check_nic_model(&nd_table[0], "stellaris");
enet = qdev_create(NULL, "stellaris_enet");
enet = qdev_new("stellaris_enet");
qdev_set_nic_properties(enet, &nd_table[0]);
qdev_init_nofail(enet);
qdev_realize_and_unref(enet, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
}

9
hw/arm/strongarm.c
View file

@ -42,6 +42,7 @@
#include "chardev/char-serial.h"
#include "sysemu/sysemu.h"
#include "hw/ssi/ssi.h"
#include "qapi/error.h"
#include "qemu/cutils.h"
#include "qemu/log.h"
@ -644,8 +645,8 @@ static DeviceState *strongarm_gpio_init(hwaddr base,
DeviceState *dev;
int i;
dev = qdev_create(NULL, TYPE_STRONGARM_GPIO);
qdev_init_nofail(dev);
dev = qdev_new(TYPE_STRONGARM_GPIO);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < 12; i++)
@ -1626,9 +1627,9 @@ StrongARMState *sa1110_init(const char *cpu_type)
s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL);
for (i = 0; sa_serial[i].io_base; i++) {
DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART);
DeviceState *dev = qdev_new(TYPE_STRONGARM_UART);
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
sa_serial[i].io_base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,

16
hw/arm/versatilepb.c
View file

@ -223,10 +223,10 @@ static void versatile_init(MachineState *machine, int board_id)
/* SDRAM at address zero. */
memory_region_add_subregion(sysmem, 0, machine->ram);
sysctl = qdev_create(NULL, "realview_sysctl");
sysctl = qdev_new("realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
qdev_init_nofail(sysctl);
qdev_realize_and_unref(sysctl, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
dev = sysbus_create_varargs("pl190", 0x10140000,
@ -245,9 +245,9 @@ static void versatile_init(MachineState *machine, int board_id)
sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
dev = qdev_create(NULL, "versatile_pci");
dev = qdev_new("versatile_pci");
busdev = SYS_BUS_DEVICE(dev);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */
sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */
sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */
@ -286,10 +286,10 @@ static void versatile_init(MachineState *machine, int board_id)
pl011_create(0x101f3000, pic[14], serial_hd(2));
pl011_create(0x10009000, sic[6], serial_hd(3));
dev = qdev_create(NULL, "pl080");
dev = qdev_new("pl080");
object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream",
&error_fatal);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, 0x10130000);
sysbus_connect_irq(busdev, 0, pic[17]);
@ -319,9 +319,9 @@ static void versatile_init(MachineState *machine, int board_id)
i2c_create_slave(i2c, "ds1338", 0x68);
/* Add PL041 AACI Interface to the LM4549 codec */
pl041 = qdev_create(NULL, "pl041");
pl041 = qdev_new("pl041");
qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
qdev_init_nofail(pl041);
qdev_realize_and_unref(pl041, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]);

16
hw/arm/vexpress.c
View file

@ -236,9 +236,9 @@ static void init_cpus(MachineState *ms, const char *cpu_type,
* this must happen after the CPUs are created because a15mpcore_priv
* wires itself up to the CPU's generic_timer gpio out lines.
*/
dev = qdev_create(NULL, privdev);
dev = qdev_new(privdev);
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, periphbase);
@ -514,7 +514,7 @@ static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name,
DriveInfo *di)
{
DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
if (di) {
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di),
@ -532,7 +532,7 @@ static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name,
qdev_prop_set_uint16(dev, "id2", 0x00);
qdev_prop_set_uint16(dev, "id3", 0x00);
qdev_prop_set_string(dev, "name", name);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return PFLASH_CFI01(dev);
@ -593,7 +593,7 @@ static void vexpress_common_init(MachineState *machine)
sys_id = 0x1190f500;
sysctl = qdev_create(NULL, "realview_sysctl");
sysctl = qdev_new("realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
qdev_prop_set_uint32(sysctl, "len-db-voltage",
@ -610,15 +610,15 @@ static void vexpress_common_init(MachineState *machine)
qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
g_free(propname);
}
qdev_init_nofail(sysctl);
qdev_realize_and_unref(sysctl, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
/* VE_SP810: not modelled */
/* VE_SERIALPCI: not modelled */
pl041 = qdev_create(NULL, "pl041");
pl041 = qdev_new("pl041");
qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
qdev_init_nofail(pl041);
qdev_realize_and_unref(pl041, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);

32
hw/arm/virt.c
View file

@ -572,14 +572,14 @@ static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
}
dev = qdev_create(NULL, TYPE_ACPI_GED);
dev = qdev_new(TYPE_ACPI_GED);
qdev_prop_set_uint32(dev, "ged-event", event);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
return dev;
}
@ -594,11 +594,11 @@ static void create_its(VirtMachineState *vms)
return;
}
dev = qdev_create(NULL, itsclass);
dev = qdev_new(itsclass);
object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3",
&error_abort);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
fdt_add_its_gic_node(vms);
@ -610,11 +610,11 @@ static void create_v2m(VirtMachineState *vms)
int irq = vms->irqmap[VIRT_GIC_V2M];
DeviceState *dev;
dev = qdev_create(NULL, "arm-gicv2m");
dev = qdev_new("arm-gicv2m");
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
qdev_prop_set_uint32(dev, "base-spi", irq);
qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
for (i = 0; i < NUM_GICV2M_SPIS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
@ -636,7 +636,7 @@ static void create_gic(VirtMachineState *vms)
gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
vms->gic = qdev_create(NULL, gictype);
vms->gic = qdev_new(gictype);
qdev_prop_set_uint32(vms->gic, "revision", type);
qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
/* Note that the num-irq property counts both internal and external
@ -671,7 +671,7 @@ static void create_gic(VirtMachineState *vms)
vms->virt);
}
}
qdev_init_nofail(vms->gic);
qdev_realize_and_unref(vms->gic, NULL, &error_fatal);
gicbusdev = SYS_BUS_DEVICE(vms->gic);
sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
if (type == 3) {
@ -754,11 +754,11 @@ static void create_uart(const VirtMachineState *vms, int uart,
int irq = vms->irqmap[uart];
const char compat[] = "arm,pl011\0arm,primecell";
const char clocknames[] = "uartclk\0apb_pclk";
DeviceState *dev = qdev_create(NULL, TYPE_PL011);
DeviceState *dev = qdev_new(TYPE_PL011);
SysBusDevice *s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
memory_region_add_subregion(mem, base,
sysbus_mmio_get_region(s, 0));
sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
@ -1173,11 +1173,11 @@ static void create_smmu(const VirtMachineState *vms,
return;
}
dev = qdev_create(NULL, "arm-smmuv3");
dev = qdev_new("arm-smmuv3");
object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
&error_abort);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < NUM_SMMU_IRQS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
@ -1253,8 +1253,8 @@ static void create_pcie(VirtMachineState *vms)
int i, ecam_id;
PCIHostState *pci;
dev = qdev_create(NULL, TYPE_GPEX_HOST);
qdev_init_nofail(dev);
dev = qdev_new(TYPE_GPEX_HOST);
qdev_realize_and_unref(dev, NULL, &error_fatal);
ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
base_ecam = vms->memmap[ecam_id].base;
@ -1372,11 +1372,11 @@ static void create_platform_bus(VirtMachineState *vms)
int i;
MemoryRegion *sysmem = get_system_memory();
dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
dev->id = TYPE_PLATFORM_BUS_DEVICE;
qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
vms->platform_bus_dev = dev;
s = SYS_BUS_DEVICE(dev);

38
hw/arm/xilinx_zynq.c
View file

@ -114,12 +114,12 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
DeviceState *dev;
SysBusDevice *s;
dev = qdev_create(NULL, TYPE_CADENCE_GEM);
dev = qdev_new(TYPE_CADENCE_GEM);
if (nd->used) {
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
qdev_set_nic_properties(dev, nd);
}
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);
@ -136,11 +136,11 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
qdev_prop_set_uint8(dev, "num-busses", num_busses);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, base_addr);
if (is_qspi) {
@ -222,8 +222,8 @@ static void zynq_init(MachineState *machine)
0);
/* Create slcr, keep a pointer to connect clocks */
slcr = qdev_create(NULL, "xilinx,zynq_slcr");
qdev_init_nofail(slcr);
slcr = qdev_new("xilinx,zynq_slcr");
qdev_realize_and_unref(slcr, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
/* Create the main clock source, and feed slcr with it */
@ -234,9 +234,9 @@ static void zynq_init(MachineState *machine)
clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
dev = qdev_new(TYPE_A9MPCORE_PRIV);
qdev_prop_set_uint32(dev, "num-cpu", 1);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
sysbus_connect_irq(busdev, 0,
@ -280,27 +280,27 @@ static void zynq_init(MachineState *machine)
* - SDIO Specification Version 2.0
* - MMC Specification Version 3.31
*/
dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
dev = qdev_new(TYPE_SYSBUS_SDHCI);
qdev_prop_set_uint8(dev, "sd-spec-version", 2);
qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true, "realized",
&error_fatal);
qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
&error_fatal);
}
dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
qdev_init_nofail(dev);
dev = qdev_new(TYPE_ZYNQ_XADC);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
dev = qdev_create(NULL, "pl330");
dev = qdev_new("pl330");
qdev_prop_set_uint8(dev, "num_chnls", 8);
qdev_prop_set_uint8(dev, "num_periph_req", 4);
qdev_prop_set_uint8(dev, "num_events", 16);
@ -312,7 +312,7 @@ static void zynq_init(MachineState *machine)
qdev_prop_set_uint8(dev, "rd_q_dep", 16);
qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, 0xF8003000);
sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
@ -320,8 +320,8 @@ static void zynq_init(MachineState *machine)
sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
}
dev = qdev_create(NULL, "xlnx.ps7-dev-cfg");
qdev_init_nofail(dev);
dev = qdev_new("xlnx.ps7-dev-cfg");
qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
sysbus_mmio_map(busdev, 0, 0xF8007000);

9
hw/arm/xlnx-versal-virt.c
View file

@ -432,9 +432,9 @@ static void create_virtio_regions(VersalVirt *s)
qemu_irq pic_irq;
pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq);
dev = qdev_create(NULL, "virtio-mmio");
dev = qdev_new("virtio-mmio");
object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev));
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(&s->soc.mr_ps, base, mr);
@ -463,10 +463,11 @@ static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
DeviceState *card;
card = qdev_create(qdev_get_child_bus(DEVICE(sd), "sd-bus"), TYPE_SD_CARD);
card = qdev_new(TYPE_SD_CARD);
object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card));
qdev_prop_set_drive(card, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
qdev_realize_and_unref(card, qdev_get_child_bus(DEVICE(sd), "sd-bus"),
&error_fatal);
}
static void versal_virt_init(MachineState *machine)

4
hw/arm/xlnx-versal.c
View file

@ -304,13 +304,13 @@ static void versal_unimp_area(Versal *s, const char *name,
MemoryRegion *mr,
hwaddr base, hwaddr size)
{
DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE);
DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
MemoryRegion *mr_dev;
qdev_prop_set_string(dev, "name", name);
qdev_prop_set_uint64(dev, "size", size);
object_property_add_child(OBJECT(s), name, OBJECT(dev));
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, NULL, &error_fatal);
mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(mr, base, mr_dev);

5
hw/arm/xlnx-zcu102.c
View file

@ -143,10 +143,9 @@ static void xlnx_zcu102_init(MachineState *machine)
error_report("No SD bus found for SD card %d", i);
exit(1);
}
carddev = qdev_create(bus, TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true, "realized",
&error_fatal);
qdev_realize_and_unref(carddev, bus, &error_fatal);
}
for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {