motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-11 03:24:58 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

tcg/arm: Use atom_and_align_for_opc

Browse source 
No change to the ultimate load/store routines yet, so some atomicity
conditions not yet honored, but plumbs the change to alignment through
the relevant functions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-04-22 06:48:58 +01:00
parent 64741d9902
commit 3e3d994276
1 changed files with 22 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

39
tcg/arm/tcg-target.c.inc
View file

@ -1323,6 +1323,7 @@ typedef struct {
TCGReg base; TCGReg base;
int index; int index;
bool index_scratch; bool index_scratch;
TCGAtomAlign aa;
} HostAddress; } HostAddress;
bool tcg_target_has_memory_bswap(MemOp memop) bool tcg_target_has_memory_bswap(MemOp memop)
@ -1379,8 +1380,26 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
{ {
TCGLabelQemuLdst *ldst = NULL; TCGLabelQemuLdst *ldst = NULL;
MemOp opc = get_memop(oi); MemOp opc = get_memop(oi);
MemOp a_bits = get_alignment_bits(opc); unsigned a_mask;
unsigned a_mask = (1 << a_bits) - 1;
#ifdef CONFIG_SOFTMMU
*h = (HostAddress){
.cond = COND_AL,
.base = addrlo,
.index = TCG_REG_R1,
.index_scratch = true,
};
#else
*h = (HostAddress){
.cond = COND_AL,
.base = addrlo,
.index = guest_base ? TCG_REG_GUEST_BASE : -1,
.index_scratch = false,
};
#endif
h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
a_mask = (1 << h->aa.align) - 1;
#ifdef CONFIG_SOFTMMU #ifdef CONFIG_SOFTMMU
int mem_index = get_mmuidx(oi); int mem_index = get_mmuidx(oi);
@ -1469,13 +1488,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
if (TARGET_LONG_BITS == 64) { if (TARGET_LONG_BITS == 64) {
tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0);
} }
*h = (HostAddress){
.cond = COND_AL,
.base = addrlo,
.index = TCG_REG_R1,
.index_scratch = true,
};
#else #else
if (a_mask) { if (a_mask) {
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
@ -1484,18 +1496,11 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst->addrlo_reg = addrlo; ldst->addrlo_reg = addrlo;
ldst->addrhi_reg = addrhi; ldst->addrhi_reg = addrhi;
/* We are expecting a_bits to max out at 7 */ /* We are expecting alignment to max out at 7 */
tcg_debug_assert(a_mask <= 0xff); tcg_debug_assert(a_mask <= 0xff);
/* tst addr, #mask */ /* tst addr, #mask */
tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
} }
*h = (HostAddress){
.cond = COND_AL,
.base = addrlo,
.index = guest_base ? TCG_REG_GUEST_BASE : -1,
.index_scratch = false,
};
#endif #endif
return ldst; return ldst;