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Machine queue + QOM fixes and cleanups

Browse source 
Bug fix:
 * numa: hmat: fix cache size check (Igor Mammedov)
 
 QOM fixes and cleanups:
 * Move QOM macros and typedefs to header files
 * Use TYPE_* constants on TypeInfo structs
 * Rename QOM type checking macros for consistency
 * Rename enum values and typedefs that conflict with QOM
   type checking amcros
 * Fix typos on QOM type checking macros
 * Delete unused QOM type checking macros that use
   non-existing typedefs
 * hvf: Add missing include
 * xen-legacy-backend: Add missing typedef XenLegacyDevice
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Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging

Machine queue + QOM fixes and cleanups

Bug fix:
* numa: hmat: fix cache size check (Igor Mammedov)

QOM fixes and cleanups:
* Move QOM macros and typedefs to header files
* Use TYPE_* constants on TypeInfo structs
* Rename QOM type checking macros for consistency
* Rename enum values and typedefs that conflict with QOM
  type checking amcros
* Fix typos on QOM type checking macros
* Delete unused QOM type checking macros that use
  non-existing typedefs
* hvf: Add missing include
* xen-legacy-backend: Add missing typedef XenLegacyDevice

# gpg: Signature made Thu 27 Aug 2020 20:20:05 BST
# gpg:                using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg:                issuer "ehabkost@redhat.com"
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/machine-next-pull-request: (53 commits)
  dc390: Use TYPE_DC390_DEVICE constant
  ppce500: Use TYPE_PPC_E500_PCI_BRIDGE constant
  tosa: Use TYPE_TOSA_MISC_GPIO constant
  xlnx-zcu102: Use TYPE_ZCU102_MACHINE constant
  sclpconsole: Use TYPE_* constants
  amd_iommu: Use TYPE_AMD_IOMMU_PCI constant
  nios2_iic: Use TYPE_ALTERA_IIC constant
  etsec: Use TYPE_ETSEC_COMMON constant
  migration: Rename class type checking macros
  swim: Rename struct SWIM to Swim
  s390-virtio-ccw: Rename S390_MACHINE_CLASS macro
  nubus: Rename class type checking macros
  vfio/pci: Move QOM macros to header
  kvm: Move QOM macros to kvm.h
  mptsas: Move QOM macros to header
  pxa2xx: Move QOM macros to header
  rocker: Move QOM macros to header
  auxbus: Move QOM macros to header
  piix: Move QOM macros to header
  virtio-serial-bus: Move QOM macros to header
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-08-28 11:05:08 +01:00
commit 3e39dac035
90 changed files with 621 additions and 621 deletions
Download patch file Download diff file Expand all files Collapse all files

62
include/hw/arm/allwinner-h3.h
View file

@ -61,37 +61,37 @@
* @see AwH3State
*/
enum {
AW_H3_SRAM_A1,
AW_H3_SRAM_A2,
AW_H3_SRAM_C,
AW_H3_SYSCTRL,
AW_H3_MMC0,
AW_H3_SID,
AW_H3_EHCI0,
AW_H3_OHCI0,
AW_H3_EHCI1,
AW_H3_OHCI1,
AW_H3_EHCI2,
AW_H3_OHCI2,
AW_H3_EHCI3,
AW_H3_OHCI3,
AW_H3_CCU,
AW_H3_PIT,
AW_H3_UART0,
AW_H3_UART1,
AW_H3_UART2,
AW_H3_UART3,
AW_H3_EMAC,
AW_H3_DRAMCOM,
AW_H3_DRAMCTL,
AW_H3_DRAMPHY,
AW_H3_GIC_DIST,
AW_H3_GIC_CPU,
AW_H3_GIC_HYP,
AW_H3_GIC_VCPU,
AW_H3_RTC,
AW_H3_CPUCFG,
AW_H3_SDRAM
AW_H3_DEV_SRAM_A1,
AW_H3_DEV_SRAM_A2,
AW_H3_DEV_SRAM_C,
AW_H3_DEV_SYSCTRL,
AW_H3_DEV_MMC0,
AW_H3_DEV_SID,
AW_H3_DEV_EHCI0,
AW_H3_DEV_OHCI0,
AW_H3_DEV_EHCI1,
AW_H3_DEV_OHCI1,
AW_H3_DEV_EHCI2,
AW_H3_DEV_OHCI2,
AW_H3_DEV_EHCI3,
AW_H3_DEV_OHCI3,
AW_H3_DEV_CCU,
AW_H3_DEV_PIT,
AW_H3_DEV_UART0,
AW_H3_DEV_UART1,
AW_H3_DEV_UART2,
AW_H3_DEV_UART3,
AW_H3_DEV_EMAC,
AW_H3_DEV_DRAMCOM,
AW_H3_DEV_DRAMCTL,
AW_H3_DEV_DRAMPHY,
AW_H3_DEV_GIC_DIST,
AW_H3_DEV_GIC_CPU,
AW_H3_DEV_GIC_HYP,
AW_H3_DEV_GIC_VCPU,
AW_H3_DEV_RTC,
AW_H3_DEV_CPUCFG,
AW_H3_DEV_SDRAM
};
/** Total number of CPU cores in the H3 SoC */

12
include/hw/arm/armsse.h
View file

@ -106,8 +106,8 @@
#include "hw/core/split-irq.h"
#include "hw/cpu/cluster.h"
#define TYPE_ARMSSE "arm-sse"
#define ARMSSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARMSSE)
#define TYPE_ARM_SSE "arm-sse"
#define ARM_SSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARM_SSE)
/*
* These type names are for specific IoTKit subsystems; other than
@ -224,9 +224,9 @@ typedef struct ARMSSEClass {
const ARMSSEInfo *info;
} ARMSSEClass;
#define ARMSSE_CLASS(klass) \
OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARMSSE)
#define ARMSSE_GET_CLASS(obj) \
OBJECT_GET_CLASS(ARMSSEClass, (obj), TYPE_ARMSSE)
#define ARM_SSE_CLASS(klass) \
OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARM_SSE)
#define ARM_SSE_GET_CLASS(obj) \
OBJECT_GET_CLASS(ARMSSEClass, (obj), TYPE_ARM_SSE)
#endif

92
include/hw/arm/aspeed_soc.h
View file

@ -87,52 +87,52 @@ typedef struct AspeedSoCClass {
OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
enum {
ASPEED_IOMEM,
ASPEED_UART1,
ASPEED_UART2,
ASPEED_UART3,
ASPEED_UART4,
ASPEED_UART5,
ASPEED_VUART,
ASPEED_FMC,
ASPEED_SPI1,
ASPEED_SPI2,
ASPEED_EHCI1,
ASPEED_EHCI2,
ASPEED_VIC,
ASPEED_SDMC,
ASPEED_SCU,
ASPEED_ADC,
ASPEED_VIDEO,
ASPEED_SRAM,
ASPEED_SDHCI,
ASPEED_GPIO,
ASPEED_GPIO_1_8V,
ASPEED_RTC,
ASPEED_TIMER1,
ASPEED_TIMER2,
ASPEED_TIMER3,
ASPEED_TIMER4,
ASPEED_TIMER5,
ASPEED_TIMER6,
ASPEED_TIMER7,
ASPEED_TIMER8,
ASPEED_WDT,
ASPEED_PWM,
ASPEED_LPC,
ASPEED_IBT,
ASPEED_I2C,
ASPEED_ETH1,
ASPEED_ETH2,
ASPEED_ETH3,
ASPEED_ETH4,
ASPEED_MII1,
ASPEED_MII2,
ASPEED_MII3,
ASPEED_MII4,
ASPEED_SDRAM,
ASPEED_XDMA,
ASPEED_EMMC,
ASPEED_DEV_IOMEM,
ASPEED_DEV_UART1,
ASPEED_DEV_UART2,
ASPEED_DEV_UART3,
ASPEED_DEV_UART4,
ASPEED_DEV_UART5,
ASPEED_DEV_VUART,
ASPEED_DEV_FMC,
ASPEED_DEV_SPI1,
ASPEED_DEV_SPI2,
ASPEED_DEV_EHCI1,
ASPEED_DEV_EHCI2,
ASPEED_DEV_VIC,
ASPEED_DEV_SDMC,
ASPEED_DEV_SCU,
ASPEED_DEV_ADC,
ASPEED_DEV_VIDEO,
ASPEED_DEV_SRAM,
ASPEED_DEV_SDHCI,
ASPEED_DEV_GPIO,
ASPEED_DEV_GPIO_1_8V,
ASPEED_DEV_RTC,
ASPEED_DEV_TIMER1,
ASPEED_DEV_TIMER2,
ASPEED_DEV_TIMER3,
ASPEED_DEV_TIMER4,
ASPEED_DEV_TIMER5,
ASPEED_DEV_TIMER6,
ASPEED_DEV_TIMER7,
ASPEED_DEV_TIMER8,
ASPEED_DEV_WDT,
ASPEED_DEV_PWM,
ASPEED_DEV_LPC,
ASPEED_DEV_IBT,
ASPEED_DEV_I2C,
ASPEED_DEV_ETH1,
ASPEED_DEV_ETH2,
ASPEED_DEV_ETH3,
ASPEED_DEV_ETH4,
ASPEED_DEV_MII1,
ASPEED_DEV_MII2,
ASPEED_DEV_MII3,
ASPEED_DEV_MII4,
ASPEED_DEV_SDRAM,
ASPEED_DEV_XDMA,
ASPEED_DEV_EMMC,
};
#endif /* ASPEED_SOC_H */

13
include/hw/arm/pxa.h
View file

@ -86,7 +86,10 @@ PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
/* pxa2xx_mmci.c */
#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
typedef struct PXA2xxMMCIState PXA2xxMMCIState;
#define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)
PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
hwaddr base,
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma);
@ -94,7 +97,11 @@ void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
qemu_irq coverswitch);
/* pxa2xx_pcmcia.c */
#define TYPE_PXA2XX_PCMCIA "pxa2xx-pcmcia"
typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
#define PXA2XX_PCMCIA(obj) \
OBJECT_CHECK(PXA2xxPCMCIAState, obj, TYPE_PXA2XX_PCMCIA)
PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
hwaddr base);
int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
@ -119,8 +126,14 @@ PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
qemu_irq irq, uint32_t page_size);
I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
typedef struct PXA2xxI2SState PXA2xxI2SState;
#define PXA2XX_I2C(obj) \
OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
#define TYPE_PXA2XX_FIR "pxa2xx-fir"
typedef struct PXA2xxFIrState PXA2xxFIrState;
#define PXA2XX_FIR(obj) OBJECT_CHECK(PXA2xxFIrState, (obj), TYPE_PXA2XX_FIR)
typedef struct {
ARMCPU *cpu;

6
include/hw/block/swim.h
View file

@ -67,10 +67,10 @@ struct SWIMCtrl {
};
#define TYPE_SWIM "swim"
#define SWIM(obj) OBJECT_CHECK(SWIM, (obj), TYPE_SWIM)
#define SWIM(obj) OBJECT_CHECK(Swim, (obj), TYPE_SWIM)
typedef struct SWIM {
typedef struct Swim {
SysBusDevice parent_obj;
SWIMCtrl ctrl;
} SWIM;
} Swim;
#endif

4
include/hw/display/macfb.h
View file

@ -40,9 +40,9 @@ typedef struct {
MacfbState macfb;
} MacfbSysBusState;
#define MACFB_NUBUS_DEVICE_CLASS(class) \
#define NUBUS_MACFB_CLASS(class) \
OBJECT_CLASS_CHECK(MacfbNubusDeviceClass, (class), TYPE_NUBUS_MACFB)
#define MACFB_NUBUS_GET_CLASS(obj) \
#define NUBUS_MACFB_GET_CLASS(obj) \
OBJECT_GET_CLASS(MacfbNubusDeviceClass, (obj), TYPE_NUBUS_MACFB)
typedef struct MacfbNubusDeviceClass {

2
include/hw/dma/i8257.h
View file

@ -5,6 +5,8 @@
#include "exec/ioport.h"
#define TYPE_I8257 "i8257"
#define I8257(obj) \
OBJECT_CHECK(I8257State, (obj), TYPE_I8257)
typedef struct I8257Regs {
int now[2];

3
include/hw/hyperv/vmbus-bridge.h
View file

@ -11,11 +11,10 @@
#define HW_HYPERV_VMBUS_BRIDGE_H
#include "hw/sysbus.h"
#include "hw/hyperv/vmbus.h"
#define TYPE_VMBUS_BRIDGE "vmbus-bridge"
typedef struct VMBus VMBus;
typedef struct VMBusBridge {
SysBusDevice parent_obj;

4
include/hw/hyperv/vmbus.h
View file

@ -26,6 +26,10 @@
#define VMBUS_DEVICE_GET_CLASS(obj) \
OBJECT_GET_CLASS(VMBusDeviceClass, (obj), TYPE_VMBUS_DEVICE)
#define TYPE_VMBUS "vmbus"
typedef struct VMBus VMBus;
#define VMBUS(obj) OBJECT_CHECK(VMBus, (obj), TYPE_VMBUS)
/*
* Object wrapping a GPADL -- GPA Descriptor List -- an array of guest physical
* pages, to be used for various buffers shared between the host and the guest.

5
include/hw/ide/ahci.h
View file

@ -53,11 +53,14 @@ typedef struct AHCIState {
typedef struct AHCIPCIState AHCIPCIState;
#define TYPE_ICH9_AHCI "ich9-ahci"
#define ICH_AHCI(obj) \
OBJECT_CHECK(AHCIPCIState, (obj), TYPE_ICH9_AHCI)
int32_t ahci_get_num_ports(PCIDevice *dev);
void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
#define TYPE_SYSBUS_AHCI "sysbus-ahci"
#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
typedef struct SysbusAHCIState {
/*< private >*/
@ -69,6 +72,8 @@ typedef struct SysbusAHCIState {
} SysbusAHCIState;
#define TYPE_ALLWINNER_AHCI "allwinner-ahci"
#define ALLWINNER_AHCI(obj) \
OBJECT_CHECK(AllwinnerAHCIState, (obj), TYPE_ALLWINNER_AHCI)
#define ALLWINNER_AHCI_MMIO_OFF 0x80
#define ALLWINNER_AHCI_MMIO_SIZE 0x80

1
include/hw/input/i8042.h
View file

@ -11,6 +11,7 @@
#include "hw/isa/isa.h"
#define TYPE_I8042 "i8042"
#define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042)
#define I8042_A20_LINE "a20"

1
include/hw/m68k/mcf_fec.h
View file

@ -11,6 +11,7 @@
#define HW_M68K_MCF_FEC_H
#define TYPE_MCF_FEC_NET "mcf-fec"
typedef struct mcf_fec_state mcf_fec_state;
#define MCF_FEC_NET(obj) OBJECT_CHECK(mcf_fec_state, (obj), TYPE_MCF_FEC_NET)
#define FEC_NUM_IRQ 13

3
include/hw/misc/auxbus.h
View file

@ -32,7 +32,10 @@ typedef struct AUXBus AUXBus;
typedef struct AUXSlave AUXSlave;
typedef enum AUXCommand AUXCommand;
typedef enum AUXReply AUXReply;
#define TYPE_AUXTOI2C "aux-to-i2c-bridge"
typedef struct AUXTOI2CState AUXTOI2CState;
#define AUXTOI2C(obj) OBJECT_CHECK(AUXTOI2CState, (obj), TYPE_AUXTOI2C)
enum AUXCommand {
WRITE_I2C = 0,

1
include/hw/nubus/nubus.h
View file

@ -29,7 +29,6 @@
#define NUBUS_BUS(obj) OBJECT_CHECK(NubusBus, (obj), TYPE_NUBUS_BUS)
#define TYPE_NUBUS_BRIDGE "nubus-bridge"
#define NUBUS_BRIDGE(obj) OBJECT_CHECK(NubusBridge, (obj), TYPE_NUBUS_BRIDGE)
typedef struct NubusBus {
BusState qbus;

1
include/hw/pci/pci.h
View file

@ -396,6 +396,7 @@ typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
#define TYPE_PCI_BUS "PCI"
typedef struct PCIBusClass PCIBusClass;
#define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
#define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
#define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)

4
include/hw/pci/pci_bus.h
View file

@ -10,14 +10,14 @@
* use accessor functions in pci.h
*/
typedef struct PCIBusClass {
struct PCIBusClass {
/*< private >*/
BusClass parent_class;
/*< public >*/
int (*bus_num)(PCIBus *bus);
uint16_t (*numa_node)(PCIBus *bus);
} PCIBusClass;
};
enum PCIBusFlags {
/* This bus is the root of a PCI domain */

4
include/hw/platform-bus.h
View file

@ -29,10 +29,6 @@ typedef struct PlatformBusDevice PlatformBusDevice;
#define TYPE_PLATFORM_BUS_DEVICE "platform-bus-device"
#define PLATFORM_BUS_DEVICE(obj) \
OBJECT_CHECK(PlatformBusDevice, (obj), TYPE_PLATFORM_BUS_DEVICE)
#define PLATFORM_BUS_DEVICE_CLASS(klass) \
OBJECT_CLASS_CHECK(PlatformBusDeviceClass, (klass), TYPE_PLATFORM_BUS_DEVICE)
#define PLATFORM_BUS_DEVICE_GET_CLASS(obj) \
OBJECT_GET_CLASS(PlatformBusDeviceClass, (obj), TYPE_PLATFORM_BUS_DEVICE)
struct PlatformBusDevice {
/*< private >*/

1
include/hw/ppc/spapr.h
View file

@ -41,6 +41,7 @@ typedef struct SpaprDimmState SpaprDimmState;
typedef struct SpaprMachineClass SpaprMachineClass;
#define TYPE_SPAPR_MACHINE "spapr-machine"
typedef struct SpaprMachineState SpaprMachineState;
#define SPAPR_MACHINE(obj) \
OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE)
#define SPAPR_MACHINE_GET_CLASS(obj) \

36
include/hw/ppc/spapr_irq.h
View file

@ -28,7 +28,7 @@
#define SPAPR_NR_XIRQS 0x1000
typedef struct SpaprMachineState SpaprMachineState;
struct SpaprMachineState;
typedef struct SpaprInterruptController SpaprInterruptController;
@ -67,20 +67,20 @@ typedef struct SpaprInterruptControllerClass {
int (*post_load)(SpaprInterruptController *intc, int version_id);
} SpaprInterruptControllerClass;
void spapr_irq_update_active_intc(SpaprMachineState *spapr);
void spapr_irq_update_active_intc(struct SpaprMachineState *spapr);
int spapr_irq_cpu_intc_create(SpaprMachineState *spapr,
int spapr_irq_cpu_intc_create(struct SpaprMachineState *spapr,
PowerPCCPU *cpu, Error **errp);
void spapr_irq_cpu_intc_reset(SpaprMachineState *spapr, PowerPCCPU *cpu);
void spapr_irq_cpu_intc_destroy(SpaprMachineState *spapr, PowerPCCPU *cpu);
void spapr_irq_print_info(SpaprMachineState *spapr, Monitor *mon);
void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers,
void spapr_irq_cpu_intc_reset(struct SpaprMachineState *spapr, PowerPCCPU *cpu);
void spapr_irq_cpu_intc_destroy(struct SpaprMachineState *spapr, PowerPCCPU *cpu);
void spapr_irq_print_info(struct SpaprMachineState *spapr, Monitor *mon);
void spapr_irq_dt(struct SpaprMachineState *spapr, uint32_t nr_servers,
void *fdt, uint32_t phandle);
uint32_t spapr_irq_nr_msis(SpaprMachineState *spapr);
int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
uint32_t spapr_irq_nr_msis(struct SpaprMachineState *spapr);
int spapr_irq_msi_alloc(struct SpaprMachineState *spapr, uint32_t num, bool align,
Error **errp);
void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num);
void spapr_irq_msi_free(struct SpaprMachineState *spapr, int irq, uint32_t num);
typedef struct SpaprIrq {
bool xics;
@ -92,13 +92,13 @@ extern SpaprIrq spapr_irq_xics_legacy;
extern SpaprIrq spapr_irq_xive;
extern SpaprIrq spapr_irq_dual;
void spapr_irq_init(SpaprMachineState *spapr, Error **errp);
int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
void spapr_irq_free(SpaprMachineState *spapr, int irq, int num);
qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq);
int spapr_irq_post_load(SpaprMachineState *spapr, int version_id);
void spapr_irq_reset(SpaprMachineState *spapr, Error **errp);
int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp);
void spapr_irq_init(struct SpaprMachineState *spapr, Error **errp);
int spapr_irq_claim(struct SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
void spapr_irq_free(struct SpaprMachineState *spapr, int irq, int num);
qemu_irq spapr_qirq(struct SpaprMachineState *spapr, int irq);
int spapr_irq_post_load(struct SpaprMachineState *spapr, int version_id);
void spapr_irq_reset(struct SpaprMachineState *spapr, Error **errp);
int spapr_irq_get_phandle(struct SpaprMachineState *spapr, void *fdt, Error **errp);
typedef int (*SpaprInterruptControllerInitKvm)(SpaprInterruptController *,
uint32_t, Error **);
@ -111,7 +111,7 @@ int spapr_irq_init_kvm(SpaprInterruptControllerInitKvm fn,
/*
* XICS legacy routines
*/
int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp);
int spapr_irq_find(struct SpaprMachineState *spapr, int num, bool align, Error **errp);
#define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp)
#endif

3
include/hw/ppc/spapr_xive.h
View file

@ -66,7 +66,8 @@ typedef struct SpaprXiveClass {
void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon);
void spapr_xive_hcall_init(SpaprMachineState *spapr);
struct SpaprMachineState;
void spapr_xive_hcall_init(struct SpaprMachineState *spapr);
void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable);
void spapr_xive_map_mmio(SpaprXive *xive);

38
include/hw/riscv/opentitan.h
View file

@ -49,25 +49,25 @@ typedef struct OpenTitanState {
} OpenTitanState;
enum {
IBEX_ROM,
IBEX_RAM,
IBEX_FLASH,
IBEX_UART,
IBEX_GPIO,
IBEX_SPI,
IBEX_FLASH_CTRL,
IBEX_RV_TIMER,
IBEX_AES,
IBEX_HMAC,
IBEX_PLIC,
IBEX_PWRMGR,
IBEX_RSTMGR,
IBEX_CLKMGR,
IBEX_PINMUX,
IBEX_ALERT_HANDLER,
IBEX_NMI_GEN,
IBEX_USBDEV,
IBEX_PADCTRL,
IBEX_DEV_ROM,
IBEX_DEV_RAM,
IBEX_DEV_FLASH,
IBEX_DEV_UART,
IBEX_DEV_GPIO,
IBEX_DEV_SPI,
IBEX_DEV_FLASH_CTRL,
IBEX_DEV_RV_TIMER,
IBEX_DEV_AES,
IBEX_DEV_HMAC,
IBEX_DEV_PLIC,
IBEX_DEV_PWRMGR,
IBEX_DEV_RSTMGR,
IBEX_DEV_CLKMGR,
IBEX_DEV_PINMUX,
IBEX_DEV_ALERT_HANDLER,
IBEX_DEV_NMI_GEN,
IBEX_DEV_USBDEV,
IBEX_DEV_PADCTRL,
};
enum {

1
include/hw/s390x/event-facility.h
View file

@ -195,6 +195,7 @@ typedef struct SCLPEventClass {
} SCLPEventClass;
#define TYPE_SCLP_EVENT_FACILITY "s390-sclp-event-facility"
typedef struct SCLPEventFacility SCLPEventFacility;
#define EVENT_FACILITY(obj) \
OBJECT_CHECK(SCLPEventFacility, (obj), TYPE_SCLP_EVENT_FACILITY)
#define EVENT_FACILITY_CLASS(klass) \

2
include/hw/s390x/s390-virtio-ccw.h
View file

@ -18,7 +18,7 @@
#define S390_CCW_MACHINE(obj) \
OBJECT_CHECK(S390CcwMachineState, (obj), TYPE_S390_CCW_MACHINE)
#define S390_MACHINE_CLASS(klass) \
#define S390_CCW_MACHINE_CLASS(klass) \
OBJECT_CLASS_CHECK(S390CcwMachineClass, (klass), TYPE_S390_CCW_MACHINE)
typedef struct S390CcwMachineState {

1
include/hw/s390x/s390_flic.h
View file

@ -75,6 +75,7 @@ typedef struct S390FLICStateClass {
} S390FLICStateClass;
#define TYPE_KVM_S390_FLIC "s390-flic-kvm"
typedef struct KVMS390FLICState KVMS390FLICState;
#define KVM_S390_FLIC(obj) \
OBJECT_CHECK(KVMS390FLICState, (obj), TYPE_KVM_S390_FLIC)

4
include/hw/s390x/sclp.h
View file

@ -185,12 +185,12 @@ typedef struct SCCB {
#define SCLP_CLASS(oc) OBJECT_CLASS_CHECK(SCLPDeviceClass, (oc), TYPE_SCLP)
#define SCLP_GET_CLASS(obj) OBJECT_GET_CLASS(SCLPDeviceClass, (obj), TYPE_SCLP)
typedef struct SCLPEventFacility SCLPEventFacility;
struct SCLPEventFacility;
typedef struct SCLPDevice {
/* private */
DeviceState parent_obj;
SCLPEventFacility *event_facility;
struct SCLPEventFacility *event_facility;
int increment_size;
/* public */

4
include/hw/southbridge/piix.h
View file

@ -64,6 +64,10 @@ typedef struct PIIXState {
MemoryRegion rcr_mem;
} PIIX3State;
#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
#define PIIX3_PCI_DEVICE(obj) \
OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
extern PCIDevice *piix4_dev;
PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);

2
include/hw/timer/aspeed_timer.h
View file

@ -26,7 +26,7 @@
#include "hw/misc/aspeed_scu.h"
#define ASPEED_TIMER(obj) \
OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER);
OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER)
#define TYPE_ASPEED_TIMER "aspeed.timer"
#define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400"
#define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500"

2
include/hw/timer/i8254.h
View file

@ -39,6 +39,8 @@ typedef struct PITChannelInfo {
} PITChannelInfo;
#define TYPE_PIT_COMMON "pit-common"
typedef struct PITCommonState PITCommonState;
typedef struct PITCommonClass PITCommonClass;
#define PIT_COMMON(obj) \
OBJECT_CHECK(PITCommonState, (obj), TYPE_PIT_COMMON)
#define PIT_COMMON_CLASS(klass) \

8
include/hw/timer/i8254_internal.h
View file

@ -50,14 +50,14 @@ typedef struct PITChannelState {
uint32_t irq_disabled;
} PITChannelState;
typedef struct PITCommonState {
struct PITCommonState {
ISADevice dev;
MemoryRegion ioports;
uint32_t iobase;
PITChannelState channels[3];
} PITCommonState;
};
typedef struct PITCommonClass {
struct PITCommonClass {
ISADeviceClass parent_class;
void (*set_channel_gate)(PITCommonState *s, PITChannelState *sc, int val);
@ -65,7 +65,7 @@ typedef struct PITCommonClass {
PITChannelInfo *info);
void (*pre_save)(PITCommonState *s);
void (*post_load)(PITCommonState *s);
} PITCommonClass;
};
int pit_get_out(PITChannelState *s, int64_t current_time);
int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time);

2
include/hw/virtio/virtio-gpu.h
View file

@ -36,6 +36,8 @@
OBJECT_CHECK(VirtIOGPU, (obj), TYPE_VIRTIO_GPU)
#define TYPE_VHOST_USER_GPU "vhost-user-gpu"
#define VHOST_USER_GPU(obj) \
OBJECT_CHECK(VhostUserGPU, (obj), TYPE_VHOST_USER_GPU)
#define VIRTIO_ID_GPU 16

5
include/hw/virtio/virtio-serial.h
View file

@ -33,7 +33,12 @@ struct virtio_serial_conf {
OBJECT_GET_CLASS(VirtIOSerialPortClass, (obj), TYPE_VIRTIO_SERIAL_PORT)
typedef struct VirtIOSerial VirtIOSerial;
#define TYPE_VIRTIO_SERIAL_BUS "virtio-serial-bus"
typedef struct VirtIOSerialBus VirtIOSerialBus;
#define VIRTIO_SERIAL_BUS(obj) \
OBJECT_CHECK(VirtIOSerialBus, (obj), TYPE_VIRTIO_SERIAL_BUS)
typedef struct VirtIOSerialPort VirtIOSerialPort;
typedef struct VirtIOSerialPortClass {

1
include/hw/xen/xen-legacy-backend.h
View file

@ -9,6 +9,7 @@
#define TYPE_XENSYSBUS "xen-sysbus"
#define TYPE_XENBACKEND "xen-backend"
typedef struct XenLegacyDevice XenLegacyDevice;
#define XENBACKEND_DEVICE(obj) \
OBJECT_CHECK(XenLegacyDevice, (obj), TYPE_XENBACKEND)