motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-12-18 05:28:36 -07:00
Code Issues Projects Releases Packages Wiki Activity Actions

Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno.

Browse source 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3146 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-08-26 17:37:23 +00:00
parent c92843b5df
commit 3ddf0b5cde
4 changed files with 32 additions and 24 deletions
Download patch file Download diff file Expand all files Collapse all files

16
target-mips/translate_init.c
View file

@ -86,7 +86,6 @@ static mips_def_t mips_defs[] =
.SYNCI_Step = 32,
.CCRes = 2,
.Status_rw_bitmask = 0x3278FF17,
.SEGBITS = 32,
},
{
.name = "4KEcR1",
@ -100,7 +99,6 @@ static mips_def_t mips_defs[] =
.SYNCI_Step = 32,
.CCRes = 2,
.Status_rw_bitmask = 0x3278FF17,
.SEGBITS = 32,
},
{
.name = "4KEc",
@ -114,7 +112,6 @@ static mips_def_t mips_defs[] =
.SYNCI_Step = 32,
.CCRes = 2,
.Status_rw_bitmask = 0x3278FF17,
.SEGBITS = 32,
},
{
.name = "24Kc",
@ -128,7 +125,6 @@ static mips_def_t mips_defs[] =
.SYNCI_Step = 32,
.CCRes = 2,
.Status_rw_bitmask = 0x3278FF17,
.SEGBITS = 32,
},
{
.name = "24Kf",
@ -144,7 +140,6 @@ static mips_def_t mips_defs[] =
.Status_rw_bitmask = 0x3678FF17,
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
.SEGBITS = 32,
},
#ifdef TARGET_MIPS64
{
@ -293,8 +288,15 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
env->Status_rw_bitmask = def->Status_rw_bitmask;
env->fcr0 = def->CP1_fcr0;
#ifdef TARGET_MIPS64
env->SEGBITS = def->SEGBITS;
env->SEGMask = (3ULL << 62) | ((1ULL << def->SEGBITS) - 1);
if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
{
env->hflags |= MIPS_HFLAG_64;
env->SEGBITS = def->SEGBITS;
env->SEGMask = (3ULL << 62) | ((1ULL << def->SEGBITS) - 1);
} else {
env->SEGBITS = 32;
env->SEGMask = 0xFFFFFFFF;
}
#endif
#ifdef CONFIG_USER_ONLY
if (env->CP0_Config1 & (1 << CP0C1_FP))