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hw/intc/aspeed: Introduce helper functions for enable and status registers

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The behavior of the enable and status registers is almost identical between
INTC(CPU Die) and INTCIO(IO Die). To reduce duplicated code, adds
"aspeed_intc_enable_handler" functions to handle enable register write
behavior and "aspeed_intc_status_handler" functions to handle status
register write behavior. No functional change.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-7-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-03-07 11:59:15 +08:00 • committed by Cédric Le Goater
parent 7ffee511fc
commit 3d6e15eafb
1 changed files with 108 additions and 83 deletions
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103
hw/intc/aspeed_intc.c
View file

@ -120,40 +120,15 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)
} }
} }
static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int size) static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset,
uint64_t data)
{ {
AspeedINTCState *s = ASPEED_INTC(opaque);
uint32_t reg = offset >> 2;
uint32_t value = 0;
value = s->regs[reg];
trace_aspeed_intc_read(offset, size, value);
return value;
}
static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
unsigned size)
{
AspeedINTCState *s = ASPEED_INTC(opaque);
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
uint32_t reg = offset >> 2; uint32_t reg = offset >> 2;
uint32_t old_enable; uint32_t old_enable;
uint32_t change; uint32_t change;
uint32_t irq; uint32_t irq;
trace_aspeed_intc_write(offset, size, data);
switch (reg) {
case R_GICINT128_EN:
case R_GICINT129_EN:
case R_GICINT130_EN:
case R_GICINT131_EN:
case R_GICINT132_EN:
case R_GICINT133_EN:
case R_GICINT134_EN:
case R_GICINT135_EN:
case R_GICINT136_EN:
irq = (offset & 0x0f00) >> 8; irq = (offset & 0x0f00) >> 8;
if (irq >= aic->num_ints) { if (irq >= aic->num_ints) {
@ -163,8 +138,9 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
} }
/* /*
* These registers are used for enable sources interrupt and * The enable registers are used to enable source interrupts.
* mask and unmask source interrupt while executing source ISR. * They also handle masking and unmasking of source interrupts
* during the execution of the source ISR.
*/ */
/* disable all source interrupt */ /* disable all source interrupt */
@ -192,17 +168,22 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
s->mask[irq] |= change; s->mask[irq] |= change;
trace_aspeed_intc_mask(change, s->mask[irq]); trace_aspeed_intc_mask(change, s->mask[irq]);
} }
s->regs[reg] = data; s->regs[reg] = data;
break; }
case R_GICINT128_STATUS:
case R_GICINT129_STATUS: static void aspeed_intc_status_handler(AspeedINTCState *s, hwaddr offset,
case R_GICINT130_STATUS: uint64_t data)
case R_GICINT131_STATUS: {
case R_GICINT132_STATUS: AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
case R_GICINT133_STATUS: uint32_t reg = offset >> 2;
case R_GICINT134_STATUS: uint32_t irq;
case R_GICINT135_STATUS:
case R_GICINT136_STATUS: if (!data) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__);
return;
}
irq = (offset & 0x0f00) >> 8; irq = (offset & 0x0f00) >> 8;
if (irq >= aic->num_ints) { if (irq >= aic->num_ints) {
@ -243,6 +224,50 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
aspeed_intc_update(s, irq, 0); aspeed_intc_update(s, irq, 0);
} }
} }
}
static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int size)
{
AspeedINTCState *s = ASPEED_INTC(opaque);
uint32_t reg = offset >> 2;
uint32_t value = 0;
value = s->regs[reg];
trace_aspeed_intc_read(offset, size, value);
return value;
}
static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
unsigned size)
{
AspeedINTCState *s = ASPEED_INTC(opaque);
uint32_t reg = offset >> 2;
trace_aspeed_intc_write(offset, size, data);
switch (reg) {
case R_GICINT128_EN:
case R_GICINT129_EN:
case R_GICINT130_EN:
case R_GICINT131_EN:
case R_GICINT132_EN:
case R_GICINT133_EN:
case R_GICINT134_EN:
case R_GICINT135_EN:
case R_GICINT136_EN:
aspeed_intc_enable_handler(s, offset, data);
break;
case R_GICINT128_STATUS:
case R_GICINT129_STATUS:
case R_GICINT130_STATUS:
case R_GICINT131_STATUS:
case R_GICINT132_STATUS:
case R_GICINT133_STATUS:
case R_GICINT134_STATUS:
case R_GICINT135_STATUS:
case R_GICINT136_STATUS:
aspeed_intc_status_handler(s, offset, data);
break; break;
default: default:
s->regs[reg] = data; s->regs[reg] = data;