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target-arm queue:

Browse source 
* New machine type: stm32vldiscovery
  * hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
  * hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
  * virt: Fix implementation of GPIO-based powerdown/shutdown mechanism
  * Correct the encoding of MDCCSR_EL0 and DBGDSCRint
  * hw/intc: Improve formatting of MEMTX_ERROR guest error message
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210709' into staging

target-arm queue:
 * New machine type: stm32vldiscovery
 * hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
 * hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
 * virt: Fix implementation of GPIO-based powerdown/shutdown mechanism
 * Correct the encoding of MDCCSR_EL0 and DBGDSCRint
 * hw/intc: Improve formatting of MEMTX_ERROR guest error message

# gpg: Signature made Fri 09 Jul 2021 17:09:10 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210709:
  hw/intc: Improve formatting of MEMTX_ERROR guest error message
  target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint
  hw/arm/stellaris: Expand comment about handling of OLED chipselect
  hw/gpio/pl061: Document a shortcoming in our implementation
  hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset
  hw/arm/virt: Make PL061 GPIO lines pulled low, not high
  hw/gpio/pl061: Make pullup/pulldown of outputs configurable
  hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
  hw/gpio/pl061: Document the interface of this device
  hw/gpio/pl061: Add tracepoints for register read and write
  hw/gpio/pl061: Clean up read/write offset handling logic
  hw/gpio/pl061: Convert DPRINTF to tracepoints
  hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
  tests/boot-serial-test: Add STM32VLDISCOVERY board testcase
  docs/system: arm: Add stm32 boards description
  stm32vldiscovery: Add the STM32VLDISCOVERY Machine
  stm32f100: Add the stm32f100 SoC

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-07-11 13:11:32 +01:00
commit 3cfcc329af
17 changed files with 790 additions and 78 deletions
Download patch file Download diff file Expand all files Collapse all files

37
tests/qtest/boot-serial-test.c
View file

@ -94,6 +94,41 @@ static const uint8_t kernel_nrf51[] = {
0x1c, 0x25, 0x00, 0x40 /* 0x4000251c = UART TXD */
};
static const uint8_t kernel_stm32vldiscovery[] = {
0x00, 0x00, 0x00, 0x00, /* Stack top address */
0x1d, 0x00, 0x00, 0x00, /* Reset handler address */
0x00, 0x00, 0x00, 0x00, /* NMI */
0x00, 0x00, 0x00, 0x00, /* Hard fault */
0x00, 0x00, 0x00, 0x00, /* Memory management fault */
0x00, 0x00, 0x00, 0x00, /* Bus fault */
0x00, 0x00, 0x00, 0x00, /* Usage fault */
0x0b, 0x4b, /* ldr r3, [pc, #44] Get RCC */
0x44, 0xf2, 0x04, 0x02, /* movw r2, #16388 */
0x1a, 0x60, /* str r2, [r3] */
0x0a, 0x4b, /* ldr r3, [pc, #40] Get GPIOA */
0x1a, 0x68, /* ldr r2, [r3] */
0x22, 0xf0, 0xf0, 0x02, /* bic r2, r2, #240 */
0x1a, 0x60, /* str r2, [r3] */
0x1a, 0x68, /* ldr r2, [r3] */
0x42, 0xf0, 0xb0, 0x02, /* orr r2, r2, #176 */
0x1a, 0x60, /* str r2, [r3] */
0x07, 0x4b, /* ldr r3, [pc, #26] Get BAUD */
0x45, 0x22, /* movs r2, #69 */
0x1a, 0x60, /* str r2, [r3] */
0x06, 0x4b, /* ldr r3, [pc, #24] Get ENABLE */
0x42, 0xf2, 0x08, 0x02, /* movw r2, #8200 */
0x1a, 0x60, /* str r2, [r3] */
0x05, 0x4b, /* ldr r3, [pc, #20] Get TXD */
0x54, 0x22, /* movs r2, 'T' */
0x1a, 0x60, /* str r2, [r3] */
0xfe, 0xe7, /* b . */
0x18, 0x10, 0x02, 0x40, /* 0x40021018 = RCC */
0x04, 0x08, 0x01, 0x40, /* 0x40010804 = GPIOA */
0x08, 0x38, 0x01, 0x40, /* 0x40013808 = USART1 BAUD */
0x0c, 0x38, 0x01, 0x40, /* 0x4001380c = USART1 ENABLE */
0x04, 0x38, 0x01, 0x40 /* 0x40013804 = USART1 TXD */
};
typedef struct testdef {
const char *arch; /* Target architecture */
const char *machine; /* Name of the machine */
@ -144,6 +179,8 @@ static testdef_t tests[] = {
{ "aarch64", "virt", "-cpu max", "TT", sizeof(kernel_aarch64),
kernel_aarch64 },
{ "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
{ "arm", "stm32vldiscovery", "", "T",
sizeof(kernel_stm32vldiscovery), kernel_stm32vldiscovery },
{ NULL }
};