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target-arm queue:

Browse source 
* New machine type: stm32vldiscovery
  * hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
  * hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
  * virt: Fix implementation of GPIO-based powerdown/shutdown mechanism
  * Correct the encoding of MDCCSR_EL0 and DBGDSCRint
  * hw/intc: Improve formatting of MEMTX_ERROR guest error message
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210709' into staging

target-arm queue:
 * New machine type: stm32vldiscovery
 * hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
 * hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
 * virt: Fix implementation of GPIO-based powerdown/shutdown mechanism
 * Correct the encoding of MDCCSR_EL0 and DBGDSCRint
 * hw/intc: Improve formatting of MEMTX_ERROR guest error message

# gpg: Signature made Fri 09 Jul 2021 17:09:10 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210709:
  hw/intc: Improve formatting of MEMTX_ERROR guest error message
  target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint
  hw/arm/stellaris: Expand comment about handling of OLED chipselect
  hw/gpio/pl061: Document a shortcoming in our implementation
  hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset
  hw/arm/virt: Make PL061 GPIO lines pulled low, not high
  hw/gpio/pl061: Make pullup/pulldown of outputs configurable
  hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
  hw/gpio/pl061: Document the interface of this device
  hw/gpio/pl061: Add tracepoints for register read and write
  hw/gpio/pl061: Clean up read/write offset handling logic
  hw/gpio/pl061: Convert DPRINTF to tracepoints
  hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
  tests/boot-serial-test: Add STM32VLDISCOVERY board testcase
  docs/system: arm: Add stm32 boards description
  stm32vldiscovery: Add the STM32VLDISCOVERY Machine
  stm32f100: Add the stm32f100 SoC

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-07-11 13:11:32 +01:00
commit 3cfcc329af
17 changed files with 790 additions and 78 deletions
Download patch file Download diff file Expand all files Collapse all files

66
docs/system/arm/stm32.rst Normal file
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@ -0,0 +1,66 @@
STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``stm32vldiscovery``)
========================================================================================
The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
STMicroelectronics.
.. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
based on this chip :
- ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcontroller
The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
based on this chip :
- ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller
The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin
compatible with STM32F2 series. The following machines are based on this chip :
- ``netduinoplus2`` Netduino Plus 2 board with STM32F405RGT6 microcontroller
There are many other STM32 series that are currently not supported by QEMU.
Supported devices
-----------------
* ARM Cortex-M3, Cortex M4F
* Analog to Digital Converter (ADC)
* EXTI interrupt
* Serial ports (USART)
* SPI controller
* System configuration (SYSCFG)
* Timer controller (TIMER)
Missing devices
---------------
* Camera interface (DCMI)
* Controller Area Network (CAN)
* Cycle Redundancy Check (CRC) calculation unit
* Digital to Analog Converter (DAC)
* DMA controller
* Ethernet controller
* Flash Interface Unit
* GPIO controller
* I2C controller
* Inter-Integrated Sound (I2S) controller
* Power supply configuration (PWR)
* Random Number Generator (RNG)
* Real-Time Clock (RTC) controller
* Reset and Clock Controller (RCC)
* Secure Digital Input/Output (SDIO) interface
* USB OTG
* Watchdog controller (IWDG, WWDG)
Boot options
------------
The STM32 machines can be started using the ``-kernel`` option to load a
firmware. Example:
.. code-block:: bash
$ qemu-system-arm -M stm32vldiscovery -kernel firmware.bin

1
docs/system/target-arm.rst
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@ -97,6 +97,7 @@ undocumented; you can get a complete list by running
arm/collie
arm/sx1
arm/stellaris
arm/stm32
arm/virt
arm/xlnx-versal-virt