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target/arm: Implement SVE compress active elements

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180613015641.5667-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-06-15 14:57:14 +01:00 • committed by Peter Maydell
parent 234b48e9c6
commit 3ca879aeb3
4 changed files with 55 additions and 0 deletions
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12
target/arm/translate-sve.c
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@ -2284,6 +2284,18 @@ static bool trans_TRN2_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
return do_zzz_data_ool(s, a, 1 << a->esz, trn_fns[a->esz]);
}
/*
*** SVE Permute Vector - Predicated Group
*/
static bool trans_COMPACT(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
static gen_helper_gvec_3 * const fns[4] = {
NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d
};
return do_zpz_ool(s, a, fns[a->esz]);
}
/*
*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
*/