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hw/riscv: Allow creating multiple instances of CLINT

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We extend CLINT emulation to allow multiple instances of CLINT in
a QEMU RISC-V machine. To achieve this, we remove first HART id
zero assumption from CLINT emulation.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-Id: <20200616032229.766089-2-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel 2020-05-14 15:51:31 +05:30 • committed by Alistair Francis
parent 7774e403f2
commit 3bf03f0899
6 changed files with 20 additions and 15 deletions
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7
include/hw/riscv/sifive_clint.h
View file

@ -33,6 +33,7 @@ typedef struct SiFiveCLINTState {
/*< public >*/
MemoryRegion mmio;
uint32_t hartid_base;
uint32_t num_harts;
uint32_t sip_base;
uint32_t timecmp_base;
@ -40,9 +41,9 @@ typedef struct SiFiveCLINTState {
uint32_t aperture_size;
} SiFiveCLINTState;
DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base,
bool provide_rdtime);
DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime);
enum {
SIFIVE_SIP_BASE = 0x0,