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target/riscv: Add smstateen support

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Smstateen extension specifies a mechanism to close
the potential covert channels that could cause security issues.

This patch adds the CSRs defined in the specification and
the corresponding predicates and read/write functions.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221016124726.102129-2-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Mayuresh Chitale 2022-10-16 18:17:22 +05:30 • committed by Alistair Francis
parent aefd1108ee
commit 3bee0e4010
4 changed files with 378 additions and 0 deletions
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21
target/riscv/machine.c
View file

@ -253,6 +253,26 @@ static int riscv_cpu_post_load(void *opaque, int version_id)
return 0;
}
static bool smstateen_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
return cpu->cfg.ext_smstateen;
}
static const VMStateDescription vmstate_smstateen = {
.name = "cpu/smtateen",
.version_id = 1,
.minimum_version_id = 1,
.needed = smstateen_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4),
VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4),
VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4),
VMSTATE_END_OF_LIST()
}
};
static bool envcfg_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
@ -364,6 +384,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_kvmtimer,
&vmstate_envcfg,
&vmstate_debug,
&vmstate_smstateen,
NULL
}
};