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target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o]
Implement the following PowerISA v3.0 instuctions: xsmaddqp[o]: VSX Scalar Multiply-Add Quad-Precision [using round to Odd] xsmsubqp[o]: VSX Scalar Multiply-Subtract Quad-Precision [using round to Odd] xsnmaddqp[o]: VSX Scalar Negative Multiply-Add Quad-Precision [using round to Odd] xsnmsubqp[o]: VSX Scalar Negative Multiply-Subtract Quad-Precision [using round to Odd] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-38-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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@ -2222,6 +2222,48 @@ VSX_MADD(xvmsubsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0)
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VSX_MADD(xvnmaddsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0)
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VSX_MADD(xvnmsubsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0)
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/*
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* VSX_MADDQ - VSX floating point quad-precision muliply/add
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* op - instruction mnemonic
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* maddflgs - flags for the float*muladd routine that control the
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* various forms (madd, msub, nmadd, nmsub)
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* ro - round to odd
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*/
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#define VSX_MADDQ(op, maddflgs, ro) \
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void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *s1, ppc_vsr_t *s2,\
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ppc_vsr_t *s3) \
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{ \
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ppc_vsr_t t = *xt; \
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\
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helper_reset_fpstatus(env); \
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\
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float_status tstat = env->fp_status; \
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set_float_exception_flags(0, &tstat); \
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if (ro) { \
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tstat.float_rounding_mode = float_round_to_odd; \
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} \
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t.f128 = float128_muladd(s1->f128, s3->f128, s2->f128, maddflgs, &tstat); \
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env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
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\
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if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
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float_invalid_op_madd(env, tstat.float_exception_flags, \
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false, GETPC()); \
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} \
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\
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helper_compute_fprf_float128(env, t.f128); \
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*xt = t; \
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do_float_check_status(env, GETPC()); \
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}
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VSX_MADDQ(XSMADDQP, MADD_FLGS, 0)
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VSX_MADDQ(XSMADDQPO, MADD_FLGS, 1)
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VSX_MADDQ(XSMSUBQP, MSUB_FLGS, 0)
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VSX_MADDQ(XSMSUBQPO, MSUB_FLGS, 1)
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VSX_MADDQ(XSNMADDQP, NMADD_FLGS, 0)
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VSX_MADDQ(XSNMADDQPO, NMADD_FLGS, 1)
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VSX_MADDQ(XSNMSUBQP, NMSUB_FLGS, 0)
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VSX_MADDQ(XSNMSUBQPO, NMSUB_FLGS, 0)
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/*
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* VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision
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* op - instruction mnemonic
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