mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-06 09:13:55 -06:00
Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf
* 'ppc-next' of git://repo.or.cz/qemu/agraf: PPC: move TLBs to their own arrays PPC: 440: Use 440 style MMU as default, so Qemu knows the MMU type PPC: E500: Use MAS registers instead of internal TLB representation PPC: Only set lower 32bits with mtmsr PPC: update openbios firmware PPC: mpc8544ds: Add hypervisor node PPC: calculate kernel,initrd,cmdline locations dynamically target-ppc: Handle memory-forced I/O controller access PPC: E500: Implement reboot controller
This commit is contained in:
Blue Swirl
commit
3b88670664
18 changed files with 493 additions and 207 deletions
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@ -322,7 +322,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUState *env)
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if (env->id_tlbs == 1)
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max *= 2;
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for (nr = 0; nr < max; nr++) {
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tlb = &env->tlb[nr].tlb6;
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tlb = &env->tlb.tlb6[nr];
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pte_invalidate(&tlb->pte0);
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}
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tlb_flush(env, 1);
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@ -339,7 +339,7 @@ static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env,
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/* Invalidate ITLB + DTLB, all ways */
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for (way = 0; way < env->nb_ways; way++) {
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nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
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tlb = &env->tlb[nr].tlb6;
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tlb = &env->tlb.tlb6[nr];
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if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
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LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr,
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env->nb_tlb, eaddr);
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@ -366,7 +366,7 @@ void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
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int nr;
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nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
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tlb = &env->tlb[nr].tlb6;
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tlb = &env->tlb.tlb6[nr];
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LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
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" PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1);
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/* Invalidate any pending reference in Qemu for this virtual address */
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@ -390,7 +390,7 @@ static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx,
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for (way = 0; way < env->nb_ways; way++) {
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nr = ppc6xx_tlb_getnum(env, eaddr, way,
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access_type == ACCESS_CODE ? 1 : 0);
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tlb = &env->tlb[nr].tlb6;
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tlb = &env->tlb.tlb6[nr];
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/* This test "emulates" the PTE index match for hardware TLBs */
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if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
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LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx
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@ -433,7 +433,7 @@ static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx,
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LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n",
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ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
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/* Update page flags */
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pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
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pte_update_flags(ctx, &env->tlb.tlb6[best].pte1, ret, rw);
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}
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return ret;
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@ -948,8 +948,24 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
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ret = -3;
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}
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} else {
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target_ulong sr;
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LOG_MMU("direct store...\n");
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/* Direct-store segment : absolutely *BUGGY* for now */
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/* Direct-store implies a 32-bit MMU.
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* Check the Segment Register's bus unit ID (BUID).
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*/
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sr = env->sr[eaddr >> 28];
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if ((sr & 0x1FF00000) >> 20 == 0x07f) {
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/* Memory-forced I/O controller interface access */
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/* If T=1 and BUID=x'07F', the 601 performs a memory access
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* to SR[28-31] LA[4-31], bypassing all protection mechanisms.
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*/
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ctx->raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF);
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ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return 0;
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}
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switch (type) {
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case ACCESS_INT:
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/* Integer load/store : only access allowed */
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@ -1032,7 +1048,7 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
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/* Default return value is no match */
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ret = -1;
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for (i = 0; i < env->nb_tlb; i++) {
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tlb = &env->tlb[i].tlbe;
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tlb = &env->tlb.tlbe[i];
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if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
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ret = i;
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break;
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@ -1049,7 +1065,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUState *env)
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int i;
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for (i = 0; i < env->nb_tlb; i++) {
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tlb = &env->tlb[i].tlbe;
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tlb = &env->tlb.tlbe[i];
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tlb->prot &= ~PAGE_VALID;
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}
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tlb_flush(env, 1);
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@ -1065,7 +1081,7 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUState *env,
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int i;
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for (i = 0; i < env->nb_tlb; i++) {
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tlb = &env->tlb[i].tlbe;
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tlb = &env->tlb.tlbe[i];
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if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
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end = tlb->EPN + tlb->size;
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for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
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@ -1090,7 +1106,7 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
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raddr = (target_phys_addr_t)-1ULL;
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pr = msr_pr;
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for (i = 0; i < env->nb_tlb; i++) {
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tlb = &env->tlb[i].tlbe;
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tlb = &env->tlb.tlbe[i];
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if (ppcemb_tlb_check(env, tlb, &raddr, address,
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env->spr[SPR_40x_PID], 0, i) < 0)
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continue;
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@ -1231,7 +1247,7 @@ static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
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ret = -1;
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raddr = (target_phys_addr_t)-1ULL;
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for (i = 0; i < env->nb_tlb; i++) {
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tlb = &env->tlb[i].tlbe;
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tlb = &env->tlb.tlbe[i];
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ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address, rw,
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access_type, i);
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if (!ret) {
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@ -1256,14 +1272,14 @@ void booke206_flush_tlb(CPUState *env, int flags, const int check_iprot)
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{
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int tlb_size;
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int i, j;
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ppc_tlb_t *tlb = env->tlb;
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ppcmas_tlb_t *tlb = env->tlb.tlbm;
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for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
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if (flags & (1 << i)) {
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tlb_size = booke206_tlb_size(env, i);
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for (j = 0; j < tlb_size; j++) {
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if (!check_iprot || !(tlb[j].tlbe.attr & MAS1_IPROT)) {
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tlb[j].tlbe.prot = 0;
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if (!check_iprot || !(tlb[j].mas1 & MAS1_IPROT)) {
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tlb[j].mas1 &= ~MAS1_VALID;
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}
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}
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}
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@ -1273,11 +1289,148 @@ void booke206_flush_tlb(CPUState *env, int flags, const int check_iprot)
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tlb_flush(env, 1);
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}
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static int mmubooke206_get_physical_address(CPUState *env, mmu_ctx_t *ctx,
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target_ulong address, int rw,
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int access_type)
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target_phys_addr_t booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb)
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{
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ppcemb_tlb_t *tlb;
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uint32_t tlbncfg;
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int tlbn = booke206_tlbm_to_tlbn(env, tlb);
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target_phys_addr_t tlbm_size;
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tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
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if (tlbncfg & TLBnCFG_AVAIL) {
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tlbm_size = (tlb->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
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} else {
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tlbm_size = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
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}
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return (1 << (tlbm_size << 1)) << 10;
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}
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/* TLB check function for MAS based SoftTLBs */
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int ppcmas_tlb_check(CPUState *env, ppcmas_tlb_t *tlb,
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target_phys_addr_t *raddrp,
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target_ulong address, uint32_t pid)
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{
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target_ulong mask;
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uint32_t tlb_pid;
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/* Check valid flag */
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if (!(tlb->mas1 & MAS1_VALID)) {
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return -1;
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}
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mask = ~(booke206_tlb_to_page_size(env, tlb) - 1);
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LOG_SWTLB("%s: TLB ADDR=0x" TARGET_FMT_lx " PID=0x%x MAS1=0x%x MAS2=0x%"
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PRIx64 " mask=0x" TARGET_FMT_lx " MAS7_3=0x%" PRIx64 " MAS8=%x\n",
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__func__, address, pid, tlb->mas1, tlb->mas2, mask, tlb->mas7_3,
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tlb->mas8);
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/* Check PID */
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tlb_pid = (tlb->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT;
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if (tlb_pid != 0 && tlb_pid != pid) {
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return -1;
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}
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/* Check effective address */
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if ((address & mask) != (tlb->mas2 & MAS2_EPN_MASK)) {
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return -1;
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}
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*raddrp = (tlb->mas7_3 & mask) | (address & ~mask);
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return 0;
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}
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static int mmubooke206_check_tlb(CPUState *env, ppcmas_tlb_t *tlb,
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target_phys_addr_t *raddr, int *prot,
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target_ulong address, int rw,
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int access_type)
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{
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int ret;
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int _prot = 0;
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if (ppcmas_tlb_check(env, tlb, raddr, address,
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env->spr[SPR_BOOKE_PID]) >= 0) {
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goto found_tlb;
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}
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if (env->spr[SPR_BOOKE_PID1] &&
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ppcmas_tlb_check(env, tlb, raddr, address,
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env->spr[SPR_BOOKE_PID1]) >= 0) {
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goto found_tlb;
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}
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if (env->spr[SPR_BOOKE_PID2] &&
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ppcmas_tlb_check(env, tlb, raddr, address,
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env->spr[SPR_BOOKE_PID2]) >= 0) {
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goto found_tlb;
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}
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LOG_SWTLB("%s: TLB entry not found\n", __func__);
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return -1;
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found_tlb:
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if (msr_pr != 0) {
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if (tlb->mas7_3 & MAS3_UR) {
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_prot |= PAGE_READ;
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}
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if (tlb->mas7_3 & MAS3_UW) {
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_prot |= PAGE_WRITE;
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}
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if (tlb->mas7_3 & MAS3_UX) {
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_prot |= PAGE_EXEC;
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}
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} else {
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if (tlb->mas7_3 & MAS3_SR) {
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_prot |= PAGE_READ;
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}
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if (tlb->mas7_3 & MAS3_SW) {
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_prot |= PAGE_WRITE;
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}
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if (tlb->mas7_3 & MAS3_SX) {
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_prot |= PAGE_EXEC;
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}
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}
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/* Check the address space and permissions */
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if (access_type == ACCESS_CODE) {
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if (msr_ir != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
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LOG_SWTLB("%s: AS doesn't match\n", __func__);
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return -1;
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}
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*prot = _prot;
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if (_prot & PAGE_EXEC) {
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LOG_SWTLB("%s: good TLB!\n", __func__);
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return 0;
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}
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LOG_SWTLB("%s: no PAGE_EXEC: %x\n", __func__, _prot);
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ret = -3;
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} else {
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if (msr_dr != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
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LOG_SWTLB("%s: AS doesn't match\n", __func__);
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return -1;
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}
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*prot = _prot;
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if ((!rw && _prot & PAGE_READ) || (rw && (_prot & PAGE_WRITE))) {
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LOG_SWTLB("%s: found TLB!\n", __func__);
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return 0;
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}
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LOG_SWTLB("%s: PAGE_READ/WRITE doesn't match: %x\n", __func__, _prot);
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ret = -2;
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}
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return ret;
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}
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static int mmubooke206_get_physical_address(CPUState *env, mmu_ctx_t *ctx,
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target_ulong address, int rw,
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int access_type)
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{
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ppcmas_tlb_t *tlb;
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target_phys_addr_t raddr;
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int i, j, ret;
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@ -1288,9 +1441,9 @@ static int mmubooke206_get_physical_address(CPUState *env, mmu_ctx_t *ctx,
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int ways = booke206_tlb_ways(env, i);
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for (j = 0; j < ways; j++) {
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tlb = booke206_get_tlbe(env, i, address, j);
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ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address, rw,
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access_type, j);
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tlb = booke206_get_tlbm(env, i, address, j);
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ret = mmubooke206_check_tlb(env, tlb, &raddr, &ctx->prot, address,
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rw, access_type);
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if (ret != -1) {
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goto found_tlb;
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}
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@ -1395,7 +1548,7 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
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rw, access_type);
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} else if (env->mmu_model == POWERPC_MMU_BOOKE206) {
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ret = mmubooke206_get_physical_address(env, ctx, eaddr, rw,
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access_type);
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access_type);
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} else {
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/* No address translation. */
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ret = check_physical(env, ctx, eaddr, rw);
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