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ppc/pnv: Add an LPAR per core machine option

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Recent POWER CPUs can operate in "LPAR per core" or "LPAR per thread"
modes. In per-core mode, some SPRs and IPI doorbells are shared between
threads in a core. In per-thread mode, supervisor and user state is
not shared between threads.

OpenPOWER systems after POWER8 use LPAR per thread mode, and it is
required for KVM. Enterprise systems use LPAR per core mode, as they
partition the machine by core.

Implement a lpar-per-core machine option for powernv machines. This
is fixed true for POWER8 machines, and defaults off for P9 and P10.

With this change, powernv8 SMT now works sufficiently to run Linux,
with a single socket. Multi-threaded KVM guests still have problems,
as does multi-socket Linux boot.

Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2024-05-24 15:02:46 +10:00
parent c889195508
commit 3b5ea01e98
6 changed files with 52 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
include/hw/ppc/pnv.h
View file

@ -77,6 +77,7 @@ struct PnvMachineClass {
const char *compat;
int compat_size;
int max_smt_threads;
bool has_lpar_per_thread;
bool quirk_tb_big_core;
void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
@ -104,6 +105,7 @@ struct PnvMachineState {
hwaddr fw_load_addr;
bool big_core;
bool lpar_per_core;
};
PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id);

1
include/hw/ppc/pnv_chip.h
View file

@ -28,6 +28,7 @@ struct PnvChip {
uint64_t ram_size;
bool big_core;
bool lpar_per_core;
uint32_t nr_cores;
uint32_t nr_threads;
uint64_t cores_mask;

1
include/hw/ppc/pnv_core.h
View file

@ -57,6 +57,7 @@ struct PnvCore {
/*< public >*/
PowerPCCPU **threads;
bool big_core;
bool lpar_per_core;
uint32_t pir;
uint32_t hwid;
uint64_t hrmor;