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target/riscv: Fix format for comments
Fix formats for multi-lines comments. Add spaces around single line comments(after "/*" and before "*/"). Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230405085813.40643-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li
Alistair Francis
parent
c45eff30cb
commit
3b57254d8a
11 changed files with 151 additions and 104 deletions
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@ -287,7 +287,7 @@ static void vext_set_tail_elems_1s(CPURISCVState *env, target_ulong vl,
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}
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/*
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*** stride: access vector element from strided memory
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* stride: access vector element from strided memory
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*/
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static void
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vext_ldst_stride(void *vd, void *v0, target_ulong base,
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@ -353,10 +353,10 @@ GEN_VEXT_ST_STRIDE(vsse32_v, int32_t, ste_w)
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GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d)
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/*
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*** unit-stride: access elements stored contiguously in memory
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* unit-stride: access elements stored contiguously in memory
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*/
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/* unmasked unit-stride load and store operation*/
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/* unmasked unit-stride load and store operation */
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static void
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vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
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vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uint32_t evl,
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@ -429,7 +429,7 @@ GEN_VEXT_ST_US(vse32_v, int32_t, ste_w)
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GEN_VEXT_ST_US(vse64_v, int64_t, ste_d)
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/*
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*** unit stride mask load and store, EEW = 1
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* unit stride mask load and store, EEW = 1
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*/
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void HELPER(vlm_v)(void *vd, void *v0, target_ulong base,
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CPURISCVState *env, uint32_t desc)
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@ -450,7 +450,7 @@ void HELPER(vsm_v)(void *vd, void *v0, target_ulong base,
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}
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/*
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*** index: access vector element from indexed memory
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* index: access vector element from indexed memory
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*/
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typedef target_ulong vext_get_index_addr(target_ulong base,
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uint32_t idx, void *vs2);
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@ -554,7 +554,7 @@ GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w)
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GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d)
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/*
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*** unit-stride fault-only-fisrt load instructions
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* unit-stride fault-only-fisrt load instructions
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*/
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static inline void
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vext_ldff(void *vd, void *v0, target_ulong base,
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@ -571,7 +571,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
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uint32_t vma = vext_vma(desc);
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target_ulong addr, offset, remain;
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/* probe every access*/
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/* probe every access */
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for (i = env->vstart; i < env->vl; i++) {
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if (!vm && !vext_elem_mask(v0, i)) {
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continue;
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@ -660,7 +660,7 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
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#define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)
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/*
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*** load and store whole register instructions
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* load and store whole register instructions
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*/
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static void
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vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
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@ -733,7 +733,7 @@ GEN_VEXT_ST_WHOLE(vs4r_v, int8_t, ste_b)
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GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
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/*
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*** Vector Integer Arithmetic Instructions
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* Vector Integer Arithmetic Instructions
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*/
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/* expand macro args before macro */
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@ -1149,8 +1149,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
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vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
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} \
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env->vstart = 0; \
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/* mask destination register are always tail-agnostic */ \
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/* set tail elements to 1s */ \
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/*
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* mask destination register are always tail-agnostic
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* set tail elements to 1s
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*/ \
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if (vta_all_1s) { \
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for (; i < total_elems; i++) { \
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vext_set_elem_mask(vd, i, 1); \
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@ -1185,8 +1187,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
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DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
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} \
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env->vstart = 0; \
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/* mask destination register are always tail-agnostic */ \
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/* set tail elements to 1s */ \
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/*
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* mask destination register are always tail-agnostic
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* set tail elements to 1s
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*/ \
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if (vta_all_1s) { \
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for (; i < total_elems; i++) { \
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vext_set_elem_mask(vd, i, 1); \
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@ -1392,8 +1396,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
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vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
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} \
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env->vstart = 0; \
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/* mask destination register are always tail-agnostic */ \
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/* set tail elements to 1s */ \
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/*
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* mask destination register are always tail-agnostic
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* set tail elements to 1s
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*/ \
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if (vta_all_1s) { \
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for (; i < total_elems; i++) { \
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vext_set_elem_mask(vd, i, 1); \
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@ -1455,8 +1461,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
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DO_OP(s2, (ETYPE)(target_long)s1)); \
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} \
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env->vstart = 0; \
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/* mask destination register are always tail-agnostic */ \
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/* set tail elements to 1s */ \
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/*
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* mask destination register are always tail-agnostic
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* set tail elements to 1s
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*/ \
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if (vta_all_1s) { \
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for (; i < total_elems; i++) { \
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vext_set_elem_mask(vd, i, 1); \
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@ -2075,7 +2083,7 @@ GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4)
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GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8)
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/*
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*** Vector Fixed-Point Arithmetic Instructions
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* Vector Fixed-Point Arithmetic Instructions
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*/
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/* Vector Single-Width Saturating Add and Subtract */
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@ -2988,7 +2996,7 @@ GEN_VEXT_VX_RM(vnclipu_wx_h, 2)
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GEN_VEXT_VX_RM(vnclipu_wx_w, 4)
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/*
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*** Vector Float Point Arithmetic Instructions
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* Vector Float Point Arithmetic Instructions
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*/
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/* Vector Single-Width Floating-Point Add/Subtract Instructions */
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#define OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
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@ -4171,8 +4179,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
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DO_OP(s2, s1, &env->fp_status)); \
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} \
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env->vstart = 0; \
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/* mask destination register are always tail-agnostic */ \
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/* set tail elements to 1s */ \
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/*
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* mask destination register are always tail-agnostic
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* set tail elements to 1s
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*/ \
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if (vta_all_1s) { \
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for (; i < total_elems; i++) { \
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vext_set_elem_mask(vd, i, 1); \
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@ -4208,8 +4218,10 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
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DO_OP(s2, (ETYPE)s1, &env->fp_status)); \
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} \
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env->vstart = 0; \
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/* mask destination register are always tail-agnostic */ \
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/* set tail elements to 1s */ \
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/*
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* mask destination register are always tail-agnostic
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* set tail elements to 1s
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*/ \
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if (vta_all_1s) { \
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for (; i < total_elems; i++) { \
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vext_set_elem_mask(vd, i, 1); \
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@ -4472,7 +4484,9 @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8)
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#define WOP_UU_B uint16_t, uint8_t, uint8_t
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#define WOP_UU_H uint32_t, uint16_t, uint16_t
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#define WOP_UU_W uint64_t, uint32_t, uint32_t
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/* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/
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/*
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* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.
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*/
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RVVCALL(OPFVV1, vfwcvt_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32)
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RVVCALL(OPFVV1, vfwcvt_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64)
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GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 4)
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@ -4559,7 +4573,7 @@ GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2)
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GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4)
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/*
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*** Vector Reduction Operations
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* Vector Reduction Operations
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*/
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/* Vector Single-Width Integer Reduction Instructions */
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#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \
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@ -4713,7 +4727,7 @@ GEN_VEXT_FRED(vfwredosum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16)
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GEN_VEXT_FRED(vfwredosum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32)
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/*
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*** Vector Mask Operations
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* Vector Mask Operations
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*/
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/* Vector Mask-Register Logical Instructions */
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#define GEN_VEXT_MASK_VV(NAME, OP) \
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@ -4733,10 +4747,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
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vext_set_elem_mask(vd, i, OP(b, a)); \
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} \
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env->vstart = 0; \
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/* mask destination register are always tail- \
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* agnostic \
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/*
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* mask destination register are always tail-agnostic
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* set tail elements to 1s
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*/ \
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/* set tail elements to 1s */ \
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if (vta_all_1s) { \
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for (; i < total_elems; i++) { \
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vext_set_elem_mask(vd, i, 1); \
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@ -4779,7 +4793,7 @@ target_ulong HELPER(vcpop_m)(void *v0, void *vs2, CPURISCVState *env,
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return cnt;
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}
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/* vfirst find-first-set mask bit*/
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/* vfirst find-first-set mask bit */
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target_ulong HELPER(vfirst_m)(void *v0, void *vs2, CPURISCVState *env,
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uint32_t desc)
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{
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@ -4844,8 +4858,10 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
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}
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}
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env->vstart = 0;
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/* mask destination register are always tail-agnostic */
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/* set tail elements to 1s */
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/*
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* mask destination register are always tail-agnostic
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* set tail elements to 1s
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*/
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if (vta_all_1s) {
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for (; i < total_elems; i++) {
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vext_set_elem_mask(vd, i, 1);
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@ -4937,7 +4953,7 @@ GEN_VEXT_VID_V(vid_v_w, uint32_t, H4)
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GEN_VEXT_VID_V(vid_v_d, uint64_t, H8)
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/*
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*** Vector Permutation Instructions
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* Vector Permutation Instructions
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*/
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/* Vector Slide Instructions */
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