mirror of
https://github.com/Motorhead1991/qemu.git
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find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in the regex.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3177 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths
parent
ef18c8839e
commit
3b46e62427
173 changed files with 1557 additions and 1557 deletions
128
arm-dis.c
128
arm-dis.c
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@ -34,7 +34,7 @@ struct thumb_opcode
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};
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/* format of the assembler string :
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%% %
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%<bitfield>d print the bitfield in decimal
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%<bitfield>x print the bitfield in hex
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@ -104,7 +104,7 @@ static struct arm_opcode arm_opcodes[] =
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{0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
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{0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
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{0xf450f000, 0xfc70f000, "pld\t%a"},
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/* V5 Instructions. */
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{0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
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{0xfa000000, 0xfe000000, "blx\t%B"},
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@ -116,7 +116,7 @@ static struct arm_opcode arm_opcodes[] =
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{0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
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{0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
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/* V5E "El Segundo" Instructions. */
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/* V5E "El Segundo" Instructions. */
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{0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"},
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{0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"},
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{0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
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@ -621,14 +621,14 @@ arm_decode_shift (given, func, stream)
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void * stream;
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{
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func (stream, "%s", arm_regnames[given & 0xf]);
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if ((given & 0xff0) != 0)
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{
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if ((given & 0x10) == 0)
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{
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int amount = (given & 0xf80) >> 7;
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int shift = (given & 0x60) >> 5;
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if (amount == 0)
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{
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if (shift == 3)
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@ -636,10 +636,10 @@ arm_decode_shift (given, func, stream)
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func (stream, ", rrx");
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return;
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}
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amount = 32;
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}
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func (stream, ", %s #%d", arm_shift[shift], amount);
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}
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else
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@ -666,7 +666,7 @@ print_insn_arm1 (pc, info, given)
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if ((given & insn->mask) == insn->value)
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{
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char * c;
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for (c = insn->assembler; *c; c++)
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{
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if (*c == '%')
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@ -682,14 +682,14 @@ print_insn_arm1 (pc, info, given)
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&& ((given & 0x02000000) == 0))
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{
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int offset = given & 0xfff;
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func (stream, "[pc");
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if (given & 0x01000000)
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{
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if ((given & 0x00800000) == 0)
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offset = - offset;
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/* Pre-indexed. */
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func (stream, ", #%d]", offset);
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@ -710,7 +710,7 @@ print_insn_arm1 (pc, info, given)
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/* ie ignore the offset. */
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offset = pc + 8;
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}
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func (stream, "\t; ");
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info->print_address_func (offset, info);
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}
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@ -767,12 +767,12 @@ print_insn_arm1 (pc, info, given)
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{
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/* PC relative with immediate offset. */
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int offset = ((given & 0xf00) >> 4) | (given & 0xf);
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if ((given & 0x00800000) == 0)
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offset = -offset;
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func (stream, "[pc, #%d]\t; ", offset);
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(*info->print_address_func)
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(offset + pc + 8, info);
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}
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@ -829,7 +829,7 @@ print_insn_arm1 (pc, info, given)
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}
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}
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break;
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case 'b':
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(*info->print_address_func)
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(BDISP (given) * 4 + pc + 8, info);
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@ -911,7 +911,7 @@ print_insn_arm1 (pc, info, given)
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{
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bfd_vma address;
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bfd_vma offset = 0;
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if (given & 0x00800000)
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/* Is signed, hi bits should be ones. */
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offset = (-1) ^ 0x00ffffff;
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@ -920,7 +920,7 @@ print_insn_arm1 (pc, info, given)
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offset += given & 0x00ffffff;
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offset <<= 2;
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address = offset + pc + 8;
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if (given & 0x01000000)
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/* H bit allows addressing to 2-byte boundaries. */
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address += 2;
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@ -976,7 +976,7 @@ print_insn_arm1 (pc, info, given)
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func (stream, "3");
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}
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break;
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case 'P':
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switch (given & 0x00080080)
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{
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@ -1040,44 +1040,44 @@ print_insn_arm1 (pc, info, given)
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{
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case '-':
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c++;
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while (*c >= '0' && *c <= '9')
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bitend = (bitend * 10) + *c++ - '0';
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if (!bitend)
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abort ();
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switch (*c)
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{
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case 'r':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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func (stream, "%s", arm_regnames[reg]);
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}
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break;
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case 'd':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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func (stream, "%d", reg);
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}
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break;
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case 'x':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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func (stream, "0x%08x", reg);
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/* Some SWI instructions have special
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meanings. */
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if ((given & 0x0fffffff) == 0x0FF00000)
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@ -1089,20 +1089,20 @@ print_insn_arm1 (pc, info, given)
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case 'X':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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func (stream, "%01x", reg & 0xf);
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}
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break;
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case 'f':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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if (reg > 7)
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func (stream, "#%s",
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arm_fp_const[reg & 7]);
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@ -1163,7 +1163,7 @@ print_insn_arm1 (pc, info, given)
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}
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break;
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default:
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abort ();
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}
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@ -1252,7 +1252,7 @@ print_insn_thumb (pc, info, given)
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if (!*c) /* Check for empty (not NULL) assembler string. */
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{
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long offset;
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info->bytes_per_chunk = 4;
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info->bytes_per_line = 4;
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@ -1274,16 +1274,16 @@ print_insn_thumb (pc, info, given)
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{
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info->bytes_per_chunk = 2;
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info->bytes_per_line = 4;
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given &= 0xffff;
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for (; *c; c++)
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{
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if (*c == '%')
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{
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int domaskpc = 0;
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int domasklr = 0;
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switch (*++c)
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{
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case '%':
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@ -1293,11 +1293,11 @@ print_insn_thumb (pc, info, given)
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case 'S':
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{
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long reg;
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reg = (given >> 3) & 0x7;
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if (given & (1 << 6))
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reg += 8;
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func (stream, "%s", arm_regnames[reg]);
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}
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break;
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@ -1305,11 +1305,11 @@ print_insn_thumb (pc, info, given)
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case 'D':
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{
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long reg;
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reg = given & 0x7;
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if (given & (1 << 7))
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reg += 8;
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func (stream, "%s", arm_regnames[reg]);
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}
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break;
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@ -1331,9 +1331,9 @@ print_insn_thumb (pc, info, given)
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{
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int started = 0;
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int reg;
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func (stream, "{");
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/* It would be nice if we could spot
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ranges, and generate the rS-rE format: */
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for (reg = 0; (reg < 8); reg++)
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@ -1370,7 +1370,7 @@ print_insn_thumb (pc, info, given)
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{
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int bitstart = *c++ - '0';
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int bitend = 0;
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while (*c >= '0' && *c <= '9')
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bitstart = (bitstart * 10) + *c++ - '0';
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@ -1379,7 +1379,7 @@ print_insn_thumb (pc, info, given)
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case '-':
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{
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long reg;
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c++;
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while (*c >= '0' && *c <= '9')
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bitend = (bitend * 10) + *c++ - '0';
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@ -1478,7 +1478,7 @@ parse_arm_disassembler_option (option)
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{
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if (option == NULL)
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return;
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if (strneq (option, "reg-names-", 10))
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{
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int i;
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@ -1491,7 +1491,7 @@ parse_arm_disassembler_option (option)
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regname_selected = i;
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break;
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}
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if (i < 0)
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fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
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}
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@ -1501,7 +1501,7 @@ parse_arm_disassembler_option (option)
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force_thumb = 0;
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else
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fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
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return;
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}
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@ -1512,7 +1512,7 @@ parse_disassembler_options (options)
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char * options;
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{
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char * space;
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if (options == NULL)
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return;
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@ -1550,25 +1550,25 @@ print_insn_arm (pc, info)
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if (info->disassembler_options)
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{
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parse_disassembler_options (info->disassembler_options);
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/* To avoid repeated parsing of these options, we remove them here. */
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info->disassembler_options = NULL;
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}
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is_thumb = force_thumb;
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if (pc & 1)
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{
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is_thumb = 1;
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pc &= ~(bfd_vma) 1;
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}
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#if 0
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if (!is_thumb && info->symbols != NULL)
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{
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if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
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{
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coff_symbol_type * cs;
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cs = coffsymbol (*info->symbols);
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is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
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|| cs->native->u.syment.n_sclass == C_THUMBSTAT
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@ -1580,15 +1580,15 @@ print_insn_arm (pc, info)
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{
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elf_symbol_type * es;
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unsigned int type;
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es = *(elf_symbol_type **)(info->symbols);
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type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
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is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT);
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}
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}
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#endif
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little = (info->endian == BFD_ENDIAN_LITTLE);
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info->bytes_per_chunk = 4;
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info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
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@ -1599,17 +1599,17 @@ print_insn_arm (pc, info)
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if (status != 0 && is_thumb)
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{
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info->bytes_per_chunk = 2;
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status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
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b[3] = b[2] = 0;
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}
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if (status != 0)
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{
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info->memory_error_func (status, pc, info);
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return -1;
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}
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given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
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}
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else
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@ -1621,13 +1621,13 @@ print_insn_arm (pc, info)
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info->memory_error_func (status, pc, info);
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return -1;
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}
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if (is_thumb)
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{
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if (pc & 0x2)
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{
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given = (b[2] << 8) | b[3];
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status = info->read_memory_func
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((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info);
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if (status != 0)
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@ -1635,7 +1635,7 @@ print_insn_arm (pc, info)
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info->memory_error_func (status, pc + 4, info);
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return -1;
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}
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given |= (b[0] << 24) | (b[1] << 16);
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}
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else
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@ -1644,7 +1644,7 @@ print_insn_arm (pc, info)
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else
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given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
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}
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if (info->flags & INSN_HAS_RELOC)
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/* If the instruction has a reloc associated with it, then
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the offset field in the instruction will actually be the
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@ -1668,7 +1668,7 @@ print_arm_disassembler_options (FILE * stream)
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fprintf (stream, _("\n\
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The following ARM specific disassembler options are supported for use with\n\
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the -M switch:\n"));
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for (i = NUM_ARM_REGNAMES; i--;)
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fprintf (stream, " reg-names-%s %*c%s\n",
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regnames[i].name,
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