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hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM cap
Now that we have every piece in place we can advertise CAP_HTM to software, allowing any HPM aware driver to make use of the counters. HPM is enabled/disabled via the 'hpm-counters' attribute. Default value is 31, max value is also 31. Setting it to zero will disable HPM support. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-10-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -2357,6 +2357,15 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
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RISCV_IOMMU_CAP_SV48X4 | RISCV_IOMMU_CAP_SV57X4;
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}
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if (s->hpm_cntrs > 0) {
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/* Clip number of HPM counters to maximum supported (31). */
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if (s->hpm_cntrs > RISCV_IOMMU_IOCOUNT_NUM) {
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s->hpm_cntrs = RISCV_IOMMU_IOCOUNT_NUM;
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}
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/* Enable hardware performance monitor interface */
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s->cap |= RISCV_IOMMU_CAP_HPM;
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}
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/* Out-of-reset translation mode: OFF (DMA disabled) BARE (passthrough) */
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s->ddtp = set_field(0, RISCV_IOMMU_DDTP_MODE, s->enable_off ?
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RISCV_IOMMU_DDTP_MODE_OFF : RISCV_IOMMU_DDTP_MODE_BARE);
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@ -2404,6 +2413,18 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
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RISCV_IOMMU_TR_REQ_CTL_GO_BUSY);
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}
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/* If HPM registers are enabled. */
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if (s->cap & RISCV_IOMMU_CAP_HPM) {
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/* +1 for cycle counter bit. */
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stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_IOCOUNTINH],
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~((2 << s->hpm_cntrs) - 1));
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stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_IOHPMCYCLES], 0);
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memset(&s->regs_ro[RISCV_IOMMU_REG_IOHPMCTR_BASE],
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0x00, s->hpm_cntrs * 8);
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memset(&s->regs_ro[RISCV_IOMMU_REG_IOHPMEVT_BASE],
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0x00, s->hpm_cntrs * 8);
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}
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/* Memory region for downstream access, if specified. */
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if (s->target_mr) {
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s->target_as = g_new0(AddressSpace, 1);
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