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hw/pci-bridge/pxb-cxl: Drop RAS capability from host bridge.

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This CXL component isn't allowed to have a RAS capability.
Whilst this should be harmless as software is not expected to look
here, good to clean it up.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240215155206.2736-1-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jonathan Cameron 2024-02-15 15:52:06 +00:00 • committed by Michael S. Tsirkin
parent a8516e5c97
commit 3a95f57211
3 changed files with 19 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

15
hw/cxl/cxl-component-utils.c
View file

@ -297,6 +297,7 @@ void cxl_component_register_init_common(uint32_t *reg_state,
caps = 3; caps = 3;
break; break;
case CXL2_ROOT_PORT: case CXL2_ROOT_PORT:
case CXL2_RC:
/* + Extended Security, + Snoop */ /* + Extended Security, + Snoop */
caps = 5; caps = 5;
break; break;
@ -326,8 +327,19 @@ void cxl_component_register_init_common(uint32_t *reg_state,
CXL_##reg##_REGISTERS_OFFSET); \ CXL_##reg##_REGISTERS_OFFSET); \
} while (0) } while (0)
switch (type) {
case CXL2_DEVICE:
case CXL2_TYPE3_DEVICE:
case CXL2_LOGICAL_DEVICE:
case CXL2_ROOT_PORT:
case CXL2_UPSTREAM_PORT:
case CXL2_DOWNSTREAM_PORT:
init_cap_reg(RAS, 2, CXL_RAS_CAPABILITY_VERSION); init_cap_reg(RAS, 2, CXL_RAS_CAPABILITY_VERSION);
ras_init_common(reg_state, write_msk); ras_init_common(reg_state, write_msk);
break;
default:
break;
}
init_cap_reg(LINK, 4, CXL_LINK_CAPABILITY_VERSION); init_cap_reg(LINK, 4, CXL_LINK_CAPABILITY_VERSION);
@ -335,9 +347,10 @@ void cxl_component_register_init_common(uint32_t *reg_state,
return; return;
} }
if (type != CXL2_ROOT_PORT) {
init_cap_reg(HDM, 5, CXL_HDM_CAPABILITY_VERSION); init_cap_reg(HDM, 5, CXL_HDM_CAPABILITY_VERSION);
hdm_init_common(reg_state, write_msk, type); hdm_init_common(reg_state, write_msk, type);
}
if (caps < 5) { if (caps < 5) {
return; return;
} }

2
hw/pci-bridge/pci_expander_bridge.c
View file

@ -290,7 +290,7 @@ static void pxb_cxl_dev_reset(DeviceState *dev)
uint32_t *write_msk = cxl_cstate->crb.cache_mem_regs_write_mask; uint32_t *write_msk = cxl_cstate->crb.cache_mem_regs_write_mask;
int dsp_count = 0; int dsp_count = 0;
cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_PORT); cxl_component_register_init_common(reg_state, write_msk, CXL2_RC);
/* /*
* The CXL specification allows for host bridges with no HDM decoders * The CXL specification allows for host bridges with no HDM decoders
* if they only have a single root port. * if they only have a single root port.

1
include/hw/cxl/cxl_component.h
View file

@ -25,6 +25,7 @@ enum reg_type {
CXL2_TYPE3_DEVICE, CXL2_TYPE3_DEVICE,
CXL2_LOGICAL_DEVICE, CXL2_LOGICAL_DEVICE,
CXL2_ROOT_PORT, CXL2_ROOT_PORT,
CXL2_RC,
CXL2_UPSTREAM_PORT, CXL2_UPSTREAM_PORT,
CXL2_DOWNSTREAM_PORT, CXL2_DOWNSTREAM_PORT,
CXL3_SWITCH_MAILBOX_CCI, CXL3_SWITCH_MAILBOX_CCI,