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Catch more MIPS FPU cornercases, fix addr.ps and mulr.ps instructions.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2841 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-05-20 13:27:58 +00:00
parent 5f30d62c26
commit 3a5b360dac
2 changed files with 31 additions and 10 deletions
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16
target-mips/translate.c
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@ -5074,10 +5074,10 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, int ft,
break;
case FOP(24, 22):
gen_op_cp1_64bitmode();
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
GEN_LOAD_FREG_FTN(WTH1, ft);
GEN_LOAD_FREG_FTN(WT0, ft);
GEN_LOAD_FREG_FTN(WTH0, ft);
GEN_LOAD_FREG_FTN(WT1, fs);
GEN_LOAD_FREG_FTN(WTH1, fs);
gen_op_float_addr_ps();
GEN_STORE_FTN_FREG(fd, WT2);
GEN_STORE_FTN_FREG(fd, WTH2);
@ -5085,10 +5085,10 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, int ft,
break;
case FOP(26, 22):
gen_op_cp1_64bitmode();
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
GEN_LOAD_FREG_FTN(WTH1, ft);
GEN_LOAD_FREG_FTN(WT0, ft);
GEN_LOAD_FREG_FTN(WTH0, ft);
GEN_LOAD_FREG_FTN(WT1, fs);
GEN_LOAD_FREG_FTN(WTH1, fs);
gen_op_float_mulr_ps();
GEN_STORE_FTN_FREG(fd, WT2);
GEN_STORE_FTN_FREG(fd, WTH2);