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target/riscv/cpu.h: spelling fix: separatly

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Fixes: 40336d5b1d "target/riscv: Add HS-mode virtual interrupt and IRQ filtering support."
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Michael Tokarev 2023-11-14 19:11:33 +03:00
parent 801faee4dd
commit 3a4e56015b
1 changed files with 2 additions and 2 deletions
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4
target/riscv/cpu.h
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@ -214,13 +214,13 @@ struct CPUArchState {
/* /*
* When mideleg[i]=0 and mvien[i]=1, sie[i] is no more * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more
* alias of mie[i] and needs to be maintained separatly. * alias of mie[i] and needs to be maintained separately.
*/ */
uint64_t sie; uint64_t sie;
/* /*
* When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more
* alias of sie[i] (mie[i]) and needs to be maintained separatly. * alias of sie[i] (mie[i]) and needs to be maintained separately.
*/ */
uint64_t vsie; uint64_t vsie;