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target-xtensa: implement RER/WER instructions

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RER and WER are privileged instructions for accessing external
registers. External register address space is local to processor core.
There's no alignment requirements, addressable units are 32-bit wide
registers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2011-11-26 15:48:41 +04:00
parent 8b912ff033
commit 3a3c9dc4ca
6 changed files with 44 additions and 3 deletions
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7
target/xtensa/cpu.h
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@ -103,6 +103,7 @@ enum {
XTENSA_OPTION_PROCESSOR_ID,
XTENSA_OPTION_DEBUG,
XTENSA_OPTION_TRACE_PORT,
XTENSA_OPTION_EXTERN_REGS,
};
enum {
@ -393,6 +394,8 @@ typedef struct CPUXtensaState {
xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
unsigned autorefill_idx;
bool runstall;
AddressSpace *address_space_er;
MemoryRegion *system_er;
int pending_irq_level; /* level of last raised IRQ */
void **irq_inputs;
XtensaCcompareTimer ccompare[MAX_NCCOMPARE];
@ -488,6 +491,10 @@ int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
void reset_mmu(CPUXtensaState *env);
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)
{
return env->system_er;
}
static inline void xtensa_select_static_vectors(CPUXtensaState *env,
unsigned n)