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target-xtensa: implement RER/WER instructions

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RER and WER are privileged instructions for accessing external
registers. External register address space is local to processor core.
There's no alignment requirements, addressable units are 32-bit wide
registers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2011-11-26 15:48:41 +04:00
parent 8b912ff033
commit 3a3c9dc4ca
6 changed files with 44 additions and 3 deletions
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6
target/xtensa/cpu.c
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@ -127,6 +127,12 @@ static void xtensa_cpu_initfn(Object *obj)
cs->env_ptr = env;
env->config = xcc->config;
env->address_space_er = g_malloc(sizeof(*env->address_space_er));
env->system_er = g_malloc(sizeof(*env->system_er));
memory_region_init_io(env->system_er, NULL, NULL, env, "er",
UINT64_C(0x100000000));
address_space_init(env->address_space_er, env->system_er, "ER");
if (tcg_enabled() && !tcg_inited) {
tcg_inited = true;
xtensa_translate_init();