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Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCG

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5185 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2008-09-09 19:02:49 +00:00
parent 6f9e38017c
commit 3a3b925d47
5 changed files with 43 additions and 31 deletions
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31
target-sparc/translate.c
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@ -4368,12 +4368,19 @@ static void disas_sparc_insn(DisasContext * dc)
tcg_gen_st_i32(cpu_tmp32, cpu_env,
offsetof(CPUState, fpr[rd]));
break;
case 0x21: /* load fsr */
case 0x21: /* ldfsr, V9 ldxfsr */
#ifdef TARGET_SPARC64
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
tcg_gen_st_i32(cpu_tmp32, cpu_env,
offsetof(CPUState, ft0));
tcg_gen_helper_0_0(helper_ldfsr);
if (rd == 1) {
tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
tcg_gen_helper_0_1(helper_ldxfsr, cpu_tmp64);
} else
#else
{
tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
tcg_gen_helper_0_1(helper_ldfsr, cpu_tmp32);
}
#endif
break;
case 0x22: /* load quad fpreg */
{
@ -4506,11 +4513,19 @@ static void disas_sparc_insn(DisasContext * dc)
tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
break;
case 0x25: /* stfsr, V9 stxfsr */
#ifdef TARGET_SPARC64
gen_address_mask(dc, cpu_addr);
tcg_gen_helper_0_0(helper_stfsr);
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
offsetof(CPUState, ft0));
tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr));
if (rd == 1)
tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
else {
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp64);
tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
}
#else
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr));
tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
#endif
break;
case 0x26:
#ifdef TARGET_SPARC64