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hw/intc/arm_gicv3: Use correct number of priority bits for the CPU

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Make the GICv3 set its number of bits of physical priority from the
implementation-specific value provided in the CPU state struct, in
the same way we already do for virtual priority bits.  Because this
would be a migration compatibility break, we provide a property
force-8-bit-prio which is enabled for 7.0 and earlier versioned board
models to retain the legacy "always use 8 bits" behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-6-peter.maydell@linaro.org
Message-id: 20220506162129.2896966-5-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-05-12 16:14:56 +01:00
parent 84597ff394
commit 39f29e5993
6 changed files with 27 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

5
hw/intc/arm_gicv3_common.c
View file

@ -563,6 +563,11 @@ static Property arm_gicv3_common_properties[] = {
DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
/*
* Compatibility property: force 8 bits of physical priority, even
* if the CPU being emulated should have fewer.
*/
DEFINE_PROP_BOOL("force-8-bit-prio", GICv3State, force_8bit_prio, 0),
DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
redist_region_count, qdev_prop_uint32, uint32_t),
DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION,

15
hw/intc/arm_gicv3_cpuif.c
View file

@ -2798,6 +2798,7 @@ void gicv3_init_cpuif(GICv3State *s)
* cpu->gic_num_lrs
* cpu->gic_vpribits
* cpu->gic_vprebits
* cpu->gic_pribits
*/
/* Note that we can't just use the GICv3CPUState as an opaque pointer
@ -2810,11 +2811,17 @@ void gicv3_init_cpuif(GICv3State *s)
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
/*
* For the moment, retain the existing behaviour of 8 priority bits;
* in a following commit we will take this from the CPU state,
* as we do for the virtual priority bits.
* The CPU implementation specifies the number of supported
* bits of physical priority. For backwards compatibility
* of migration, we have a compat property that forces use
* of 8 priority bits regardless of what the CPU really has.
*/
cs->pribits = 8;
if (s->force_8bit_prio) {
cs->pribits = 8;
} else {
cs->pribits = cpu->gic_pribits ?: 5;
}
/*
* The GICv3 has separate ID register fields for virtual priority
* and preemption bit values, but only a single ID register field