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Fix BD flag handling, cause register contents, implement some more bits

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for R2 interrupt handling.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2493 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-03-18 12:43:40 +00:00
parent 36f696517b
commit 39d51eb8bc
4 changed files with 28 additions and 13 deletions
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13
hw/mips_int.c
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@ -20,20 +20,15 @@ void cpu_mips_update_irq(CPUState *env)
void cpu_mips_irq_request(void *opaque, int irq, int level)
{
CPUState *env = first_cpu;
uint32_t mask;
CPUState *env = (CPUState *)opaque;
if (irq >= 16)
if (irq < 0 || irq > 7)
return;
mask = 1 << (irq + CP0Ca_IP);
if (level) {
env->CP0_Cause |= mask;
env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
} else {
env->CP0_Cause &= ~mask;
env->CP0_Cause &= ~(1 << (irq +CP0Ca_IP));
}
cpu_mips_update_irq(env);
}