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target/microblaze: Convert dec_bit to decodetree
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
e98651d9ca
commit
39cf386458
2 changed files with 95 additions and 73 deletions
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@ -241,6 +241,21 @@ static bool do_typea(DisasContext *dc, arg_typea *arg, bool side_effects,
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return true;
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}
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static bool do_typea0(DisasContext *dc, arg_typea0 *arg, bool side_effects,
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void (*fn)(TCGv_i32, TCGv_i32))
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{
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TCGv_i32 rd, ra;
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if (arg->rd == 0 && !side_effects) {
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return true;
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}
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rd = reg_for_write(dc, arg->rd);
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ra = reg_for_read(dc, arg->ra);
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fn(rd, ra);
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return true;
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}
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static bool do_typeb_imm(DisasContext *dc, arg_typeb *arg, bool side_effects,
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void (*fni)(TCGv_i32, TCGv_i32, int32_t))
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{
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@ -283,6 +298,14 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects,
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static bool trans_##NAME(DisasContext *dc, arg_typea *a) \
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{ return dc->cpu->cfg.CFG && do_typea(dc, a, SE, FN); }
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#define DO_TYPEA0(NAME, SE, FN) \
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static bool trans_##NAME(DisasContext *dc, arg_typea0 *a) \
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{ return do_typea0(dc, a, SE, FN); }
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#define DO_TYPEA0_CFG(NAME, CFG, SE, FN) \
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static bool trans_##NAME(DisasContext *dc, arg_typea0 *a) \
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{ return dc->cpu->cfg.CFG && do_typea0(dc, a, SE, FN); }
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#define DO_TYPEBI(NAME, SE, FNI) \
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static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \
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{ return do_typeb_imm(dc, a, SE, FNI); }
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@ -345,6 +368,13 @@ DO_TYPEBI(andi, false, tcg_gen_andi_i32)
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DO_TYPEA(andn, false, tcg_gen_andc_i32)
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DO_TYPEBI(andni, false, gen_andni)
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static void gen_clz(TCGv_i32 out, TCGv_i32 ina)
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{
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tcg_gen_clzi_i32(out, ina, 32);
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}
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DO_TYPEA0_CFG(clz, use_pcmp_instr, false, gen_clz)
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static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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{
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TCGv_i32 lt = tcg_temp_new_i32();
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@ -474,6 +504,51 @@ DO_TYPEBV(rsubic, true, gen_rsubc)
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DO_TYPEBV(rsubik, false, gen_rsubk)
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DO_TYPEBV(rsubikc, true, gen_rsubkc)
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DO_TYPEA0(sext8, false, tcg_gen_ext8s_i32)
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DO_TYPEA0(sext16, false, tcg_gen_ext16s_i32)
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static void gen_sra(TCGv_i32 out, TCGv_i32 ina)
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{
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tcg_gen_andi_i32(cpu_msr_c, ina, 1);
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tcg_gen_sari_i32(out, ina, 1);
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}
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static void gen_src(TCGv_i32 out, TCGv_i32 ina)
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_mov_i32(tmp, cpu_msr_c);
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tcg_gen_andi_i32(cpu_msr_c, ina, 1);
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tcg_gen_extract2_i32(out, ina, tmp, 1);
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tcg_temp_free_i32(tmp);
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}
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static void gen_srl(TCGv_i32 out, TCGv_i32 ina)
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{
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tcg_gen_andi_i32(cpu_msr_c, ina, 1);
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tcg_gen_shri_i32(out, ina, 1);
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}
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DO_TYPEA0(sra, false, gen_sra)
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DO_TYPEA0(src, false, gen_src)
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DO_TYPEA0(srl, false, gen_srl)
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static void gen_swaph(TCGv_i32 out, TCGv_i32 ina)
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{
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tcg_gen_rotri_i32(out, ina, 16);
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}
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DO_TYPEA0(swapb, false, tcg_gen_bswap32_i32)
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DO_TYPEA0(swaph, false, gen_swaph)
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static bool trans_wdic(DisasContext *dc, arg_wdic *a)
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{
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/* Cache operations are nops: only check for supervisor mode. */
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trap_userspace(dc, true);
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return true;
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}
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DO_TYPEA(xor, false, tcg_gen_xor_i32)
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DO_TYPEBI(xori, false, tcg_gen_xori_i32)
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@ -754,78 +829,6 @@ static void dec_barrel(DisasContext *dc)
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}
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}
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static void dec_bit(DisasContext *dc)
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{
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CPUState *cs = CPU(dc->cpu);
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TCGv_i32 t0;
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unsigned int op;
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op = dc->ir & ((1 << 9) - 1);
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switch (op) {
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case 0x21:
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/* src. */
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t0 = tcg_temp_new_i32();
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tcg_gen_shli_i32(t0, cpu_msr_c, 31);
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tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1);
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if (dc->rd) {
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tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1);
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tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->rd], t0);
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}
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tcg_temp_free_i32(t0);
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break;
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case 0x1:
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case 0x41:
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/* srl. */
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tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1);
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if (dc->rd) {
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if (op == 0x41)
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tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1);
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else
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tcg_gen_sari_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1);
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}
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break;
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case 0x60:
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tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
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break;
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case 0x61:
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tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
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break;
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case 0x64:
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case 0x66:
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case 0x74:
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case 0x76:
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/* wdc. */
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trap_userspace(dc, true);
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break;
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case 0x68:
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/* wic. */
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trap_userspace(dc, true);
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break;
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case 0xe0:
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if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) {
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return;
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}
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if (dc->cpu->cfg.use_pcmp_instr) {
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tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32);
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}
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break;
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case 0x1e0:
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/* swapb */
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tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
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break;
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case 0x1e2:
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/*swaph */
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tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16);
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break;
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default:
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cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
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(uint32_t)dc->base.pc_next, op, dc->rd, dc->ra, dc->rb);
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break;
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}
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}
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static inline void sync_jmpstate(DisasContext *dc)
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{
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if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
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@ -1548,7 +1551,6 @@ static struct decoder_info {
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};
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void (*dec)(DisasContext *dc);
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} decinfo[] = {
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{DEC_BIT, dec_bit},
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{DEC_BARREL, dec_barrel},
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{DEC_LD, dec_load},
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{DEC_ST, dec_store},
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