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target-arm: Prepare translation for AArch64 code
This patch adds all the prerequisites for AArch64 support that didn't fit into split up patches. It extends important bits in the core cpu headers to also take AArch64 mode into account. Add new ARM_TBFLAG_AARCH64_STATE translation buffer flag indicate an ARMv8 cpu running in aarch64 mode vs aarch32 mode. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-10-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-4-git-send-email-john.rigby@linaro.org [PMM: * rearranged tbflags so AArch64? is bit 31 and if it is set then 30..0 are freely available for whatever makes most sense for that mode * added version bump since we change VFP migration state * added a comment about how VFP/Neon register state works * physical address space is 48 bits, not 64 * added ARM_FEATURE_AARCH64 flag to identify 64-bit capable CPUs ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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5 changed files with 151 additions and 38 deletions
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@ -37,11 +37,11 @@ static const VMStateInfo vmstate_fpscr = {
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static const VMStateDescription vmstate_vfp = {
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.name = "cpu/vfp",
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.version_id = 2,
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.minimum_version_id = 2,
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.minimum_version_id_old = 2,
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.version_id = 3,
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.minimum_version_id = 3,
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.minimum_version_id_old = 3,
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.fields = (VMStateField[]) {
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VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 32),
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VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
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/* The xregs array is a little awkward because element 1 (FPSCR)
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* requires a specific accessor, so we have to split it up in
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* the vmstate:
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