motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-09 10:34:58 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/x86: Set FloatInfZeroNaNRule explicitly

Browse source 
Set the FloatInfZeroNaNRule explicitly for the x86 target.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2024-12-11 15:30:55 +00:00
parent 67c0df045e
commit 390df9046b
2 changed files with 8 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
fpu/softfloat-specialize.c.inc
View file

@ -490,7 +490,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
* Temporarily fall back to ifdef ladder
*/
#if defined(TARGET_HPPA) || \
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
defined(TARGET_LOONGARCH)
/*
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
* case sets InvalidOp and returns the input value 'c'