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target/hexagon: Set default NaN pattern explicitly

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Set the default NaN pattern explicitly for hexagon.
Remove the ifdef from parts64_default_nan(); the only
remaining unconverted targets all use the default case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241202131347.498124-52-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2024-12-11 15:31:07 +00:00
parent b9aa1e5658
commit 38ea9ade29
2 changed files with 2 additions and 5 deletions
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5
fpu/softfloat-specialize.c.inc
View file

@ -136,10 +136,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
uint8_t dnan_pattern = status->default_nan_pattern;
if (dnan_pattern == 0) {
#if defined(TARGET_HEXAGON)
/* Sign bit set, all frac bits set. */
dnan_pattern = 0b11111111;
#else
/*
* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
* S390, SH4, TriCore, and Xtensa. Our other supported targets
@ -152,7 +148,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
/* sign bit clear, set frac msb */
dnan_pattern = 0b01000000;
}
#endif
}
assert(dnan_pattern != 0);

2
target/hexagon/cpu.c
View file

@ -286,6 +286,8 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
set_default_nan_mode(1, &env->fp_status);
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
/* Default NaN value: sign bit set, all frac bits set */
set_float_default_nan_pattern(0b11111111, &env->fp_status);
}
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)