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hw/intc/aspeed: Add Support for AST2700 INTCIO Controller

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Introduce a new ast2700 INTCIO class to support AST2700 INTCIO.
Added new register definitions for INTCIO, including enable and status
registers for IRQs GICINT192 through GICINT197.
Created a dedicated IRQ array for INTCIO, supporting six input pins and six
output pins, aligning with the newly defined registers.
Implemented "aspeed_intcio_read" and "aspeed_intcio_write" to handle
INTCIO-specific register access.

 To GICINT196                                                                                |

       ETH1    |-----------|                    |--------------------------|
      -------->|0          |                    |         INTCIO           |
       ETH2    |          4|   orgates[0]------>|inpin[0]-------->outpin[0]|
      -------->|1         5|   orgates[1]------>|inpin[1]-------->outpin[1]|
       ETH3    |          6|   orgates[2]------>|inpin[2]-------->outpin[2]|
      -------->|2        19|   orgates[3]------>|inpin[3]-------->outpin[3]|
       UART0   |         20|-->orgates[4]------>|inpin[4]-------->outpin[4]|
      -------->|7        21|   orgates[5]------>|inpin[5]-------->outpin[5]|
       UART1   |         22|                    |--------------------------|
      -------->|8        23|
       UART2   |         24|
      -------->|9        25|
       UART3   |         26|
      ---------|10       27|
       UART5   |         28|
      -------->|11       29|
       UART6   |           |
      -------->|12       30|
       UART7   |         31|
      -------->|13         |
       UART8   |  OR[0:31] |
      -------->|14         |
       UART9   |           |
      -------->|15         |
       UART10  |           |
      -------->|16         |
       UART11  |           |
      -------->|17         |
       UART12  |           |
      -------->|18         |
               |-----------|

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-18-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-03-07 11:59:26 +08:00 • committed by Cédric Le Goater
parent 9178ff91f3
commit 38ba38d87d
2 changed files with 113 additions and 0 deletions
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112
hw/intc/aspeed_intc.c
View file

@ -42,6 +42,26 @@ REG32(GICINT136_STATUS, 0x804)
REG32(GICINT192_201_EN, 0xB00) REG32(GICINT192_201_EN, 0xB00)
REG32(GICINT192_201_STATUS, 0xB04) REG32(GICINT192_201_STATUS, 0xB04)
/*
* INTCIO Registers
*
* values below are offset by - 0x100 from datasheet
* because its memory region is start at 0x100
*
*/
REG32(GICINT192_EN, 0x00)
REG32(GICINT192_STATUS, 0x04)
REG32(GICINT193_EN, 0x10)
REG32(GICINT193_STATUS, 0x14)
REG32(GICINT194_EN, 0x20)
REG32(GICINT194_STATUS, 0x24)
REG32(GICINT195_EN, 0x30)
REG32(GICINT195_STATUS, 0x34)
REG32(GICINT196_EN, 0x40)
REG32(GICINT196_STATUS, 0x44)
REG32(GICINT197_EN, 0x50)
REG32(GICINT197_STATUS, 0x54)
static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic, static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
uint32_t reg) uint32_t reg)
{ {
@ -432,6 +452,55 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
return; return;
} }
static uint64_t aspeed_intcio_read(void *opaque, hwaddr offset,
unsigned int size)
{
AspeedINTCState *s = ASPEED_INTC(opaque);
const char *name = object_get_typename(OBJECT(s));
uint32_t reg = offset >> 2;
uint32_t value = 0;
value = s->regs[reg];
trace_aspeed_intc_read(name, offset, size, value);
return value;
}
static void aspeed_intcio_write(void *opaque, hwaddr offset, uint64_t data,
unsigned size)
{
AspeedINTCState *s = ASPEED_INTC(opaque);
const char *name = object_get_typename(OBJECT(s));
uint32_t reg = offset >> 2;
trace_aspeed_intc_write(name, offset, size, data);
switch (reg) {
case R_GICINT192_EN:
case R_GICINT193_EN:
case R_GICINT194_EN:
case R_GICINT195_EN:
case R_GICINT196_EN:
case R_GICINT197_EN:
aspeed_intc_enable_handler(s, offset, data);
break;
case R_GICINT192_STATUS:
case R_GICINT193_STATUS:
case R_GICINT194_STATUS:
case R_GICINT195_STATUS:
case R_GICINT196_STATUS:
case R_GICINT197_STATUS:
aspeed_intc_status_handler(s, offset, data);
break;
default:
s->regs[reg] = data;
break;
}
return;
}
static const MemoryRegionOps aspeed_intc_ops = { static const MemoryRegionOps aspeed_intc_ops = {
.read = aspeed_intc_read, .read = aspeed_intc_read,
.write = aspeed_intc_write, .write = aspeed_intc_write,
@ -442,6 +511,16 @@ static const MemoryRegionOps aspeed_intc_ops = {
} }
}; };
static const MemoryRegionOps aspeed_intcio_ops = {
.read = aspeed_intcio_read,
.write = aspeed_intcio_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
}
};
static void aspeed_intc_instance_init(Object *obj) static void aspeed_intc_instance_init(Object *obj)
{ {
AspeedINTCState *s = ASPEED_INTC(obj); AspeedINTCState *s = ASPEED_INTC(obj);
@ -567,10 +646,43 @@ static const TypeInfo aspeed_2700_intc_info = {
.class_init = aspeed_2700_intc_class_init, .class_init = aspeed_2700_intc_class_init,
}; };
static AspeedINTCIRQ aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
{0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS},
{1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS},
{2, 2, 1, R_GICINT194_EN, R_GICINT194_STATUS},
{3, 3, 1, R_GICINT195_EN, R_GICINT195_STATUS},
{4, 4, 1, R_GICINT196_EN, R_GICINT196_STATUS},
{5, 5, 1, R_GICINT197_EN, R_GICINT197_STATUS},
};
static void aspeed_2700_intcio_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
dc->desc = "ASPEED 2700 INTC IO Controller";
aic->num_lines = 32;
aic->num_inpins = 6;
aic->num_outpins = 6;
aic->mem_size = 0x400;
aic->nr_regs = 0x58 >> 2;
aic->reg_offset = 0x100;
aic->reg_ops = &aspeed_intcio_ops;
aic->irq_table = aspeed_2700_intcio_irqs;
aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcio_irqs);
}
static const TypeInfo aspeed_2700_intcio_info = {
.name = TYPE_ASPEED_2700_INTCIO,
.parent = TYPE_ASPEED_INTC,
.class_init = aspeed_2700_intcio_class_init,
};
static void aspeed_intc_register_types(void) static void aspeed_intc_register_types(void)
{ {
type_register_static(&aspeed_intc_info); type_register_static(&aspeed_intc_info);
type_register_static(&aspeed_2700_intc_info); type_register_static(&aspeed_2700_intc_info);
type_register_static(&aspeed_2700_intcio_info);
} }
type_init(aspeed_intc_register_types); type_init(aspeed_intc_register_types);

1
include/hw/intc/aspeed_intc.h
View file

@ -14,6 +14,7 @@
#define TYPE_ASPEED_INTC "aspeed.intc" #define TYPE_ASPEED_INTC "aspeed.intc"
#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700" #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
#define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC) OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
#define ASPEED_INTC_MAX_INPINS 10 #define ASPEED_INTC_MAX_INPINS 10