mirror of
https://github.com/Motorhead1991/qemu.git
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target-arm queue:
* hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes
* handle some UNALLOCATED decode cases correctly rather
than asserting
* hw: virt: consider hw_compat_6_0
* hw/arm: add quanta-gbs-bmc machine
* hw/intc/armv7m_nvic: Remove stale comment
* target/arm: Fix mte page crossing test
* hw/arm: quanta-q71l add pca954x muxes
* target/arm: First few parts of MVE support
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210616' into staging
target-arm queue:
* hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes
* handle some UNALLOCATED decode cases correctly rather
than asserting
* hw: virt: consider hw_compat_6_0
* hw/arm: add quanta-gbs-bmc machine
* hw/intc/armv7m_nvic: Remove stale comment
* target/arm: Fix mte page crossing test
* hw/arm: quanta-q71l add pca954x muxes
* target/arm: First few parts of MVE support
# gpg: Signature made Wed 16 Jun 2021 14:34:49 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210616: (25 commits)
include/qemu/int128.h: Add function to create Int128 from int64_t
bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations
target/arm: Move expand_pred_b() data to vec_helper.c
target/arm: Add framework for MVE decode
target/arm: Implement MVE LETP insn
target/arm: Implement MVE DLSTP
target/arm: Implement MVE WLSTP insn
target/arm: Implement MVE LCTP
target/arm: Let vfp_access_check() handle late NOCP checks
target/arm: Add handling for PSR.ECI/ICI
target/arm: Handle VPR semantics in existing code
target/arm: Enable FPSCR.QC bit for MVE
target/arm: Provide and use H8 and H1_8 macros
hw/arm: quanta-q71l add pca954x muxes
hw/arm: gsj add pca9548
hw/arm: gsj add i2c comments
target/arm: Fix mte page crossing test
hw/intc/armv7m_nvic: Remove stale comment
hw/arm: quanta-gbs-bmc add i2c comments
hw/arm: add quanta-gbs-bmc machine
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
38848ce565
26 changed files with 967 additions and 348 deletions
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@ -378,6 +378,7 @@ config NPCM7XX
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select SERIAL
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select SSI
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select UNIMP
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select PCA954X
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config FSL_IMX25
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bool
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@ -413,6 +414,7 @@ config ASPEED_SOC
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select PCA9552
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select SERIAL
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select SMBUS_EEPROM
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select PCA954X
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select SSI
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select SSI_M25P80
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select TMP105
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@ -14,6 +14,7 @@
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#include "hw/arm/boot.h"
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#include "hw/arm/aspeed.h"
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#include "hw/arm/aspeed_soc.h"
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#include "hw/i2c/i2c_mux_pca954x.h"
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#include "hw/i2c/smbus_eeprom.h"
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#include "hw/misc/pca9552.h"
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#include "hw/misc/tmp105.h"
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@ -461,14 +462,18 @@ static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
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/* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
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/* TODO: Add Memory Riser i2c mux and eeproms. */
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/* TODO: i2c-2: pca9546@74 */
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/* TODO: i2c-2: pca9548@77 */
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
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/* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
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/* TODO: i2c-7: Add pca9546@70 */
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/* i2c-7 */
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
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/* - i2c@0: pmbus@59 */
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/* - i2c@1: pmbus@58 */
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/* - i2c@2: pmbus@58 */
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/* - i2c@3: pmbus@59 */
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/* TODO: i2c-7: Add PDB FRU eeprom@52 */
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/* TODO: i2c-8: Add BMC FRU eeprom@50 */
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}
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@ -18,6 +18,7 @@
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#include "hw/arm/npcm7xx.h"
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#include "hw/core/cpu.h"
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#include "hw/i2c/i2c_mux_pca954x.h"
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#include "hw/i2c/smbus_eeprom.h"
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#include "hw/loader.h"
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#include "hw/qdev-core.h"
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@ -29,6 +30,7 @@
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#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7
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#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
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#define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff
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static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
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@ -220,7 +222,18 @@ static void quanta_gsj_i2c_init(NPCM7xxState *soc)
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at24c_eeprom_init(soc, 9, 0x55, 8192);
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at24c_eeprom_init(soc, 10, 0x55, 8192);
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/* TODO: Add additional i2c devices. */
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/*
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* i2c-11:
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* - power-brick@36: delta,dps800
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* - hotswap@15: ti,lm5066i
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*/
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/*
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* i2c-12:
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* - ucd90160@6b
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*/
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i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 15), "pca9548", 0x75);
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}
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static void quanta_gsj_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc)
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@ -237,6 +250,65 @@ static void quanta_gsj_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc)
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npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
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}
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static void quanta_gbs_i2c_init(NPCM7xxState *soc)
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{
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/*
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* i2c-0:
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* pca9546@71
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*
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* i2c-1:
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* pca9535@24
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* pca9535@20
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* pca9535@21
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* pca9535@22
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* pca9535@23
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* pca9535@25
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* pca9535@26
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*
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* i2c-2:
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* sbtsi@4c
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*
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* i2c-5:
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* atmel,24c64@50 mb_fru
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* pca9546@71
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* - channel 0: max31725@54
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* - channel 1: max31725@55
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* - channel 2: max31725@5d
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* atmel,24c64@51 fan_fru
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* - channel 3: atmel,24c64@52 hsbp_fru
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*
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* i2c-6:
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* pca9545@73
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*
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* i2c-7:
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* pca9545@72
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*
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* i2c-8:
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* adi,adm1272@10
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*
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* i2c-9:
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* pca9546@71
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* - channel 0: isil,isl68137@60
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* - channel 1: isil,isl68137@61
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* - channel 2: isil,isl68137@63
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* - channel 3: isil,isl68137@45
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*
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* i2c-10:
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* pca9545@71
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*
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* i2c-11:
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* pca9545@76
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*
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* i2c-12:
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* maxim,max34451@4e
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* isil,isl68137@5d
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* isil,isl68137@5e
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*
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* i2c-14:
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* pca9545@70
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*/
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}
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static void npcm750_evb_init(MachineState *machine)
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{
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NPCM7xxState *soc;
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@ -268,6 +340,23 @@ static void quanta_gsj_init(MachineState *machine)
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npcm7xx_load_kernel(machine, soc);
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}
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static void quanta_gbs_init(MachineState *machine)
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{
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NPCM7xxState *soc;
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soc = npcm7xx_create_soc(machine, QUANTA_GBS_POWER_ON_STRAPS);
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npcm7xx_connect_dram(soc, machine->ram);
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qdev_realize(DEVICE(soc), NULL, &error_fatal);
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npcm7xx_load_bootrom(machine, soc);
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npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f",
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drive_get(IF_MTD, 0, 0));
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quanta_gbs_i2c_init(soc);
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npcm7xx_load_kernel(machine, soc);
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}
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static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type)
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{
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NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type));
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@ -316,6 +405,18 @@ static void gsj_machine_class_init(ObjectClass *oc, void *data)
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mc->default_ram_size = 512 * MiB;
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};
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static void gbs_bmc_machine_class_init(ObjectClass *oc, void *data)
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{
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NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
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MachineClass *mc = MACHINE_CLASS(oc);
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npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
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mc->desc = "Quanta GBS (Cortex-A9)";
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mc->init = quanta_gbs_init;
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mc->default_ram_size = 1 * GiB;
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}
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static const TypeInfo npcm7xx_machine_types[] = {
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{
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.name = TYPE_NPCM7XX_MACHINE,
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@ -332,6 +433,10 @@ static const TypeInfo npcm7xx_machine_types[] = {
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.name = MACHINE_TYPE_NAME("quanta-gsj"),
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.parent = TYPE_NPCM7XX_MACHINE,
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.class_init = gsj_machine_class_init,
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}, {
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.name = MACHINE_TYPE_NAME("quanta-gbs-bmc"),
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.parent = TYPE_NPCM7XX_MACHINE,
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.class_init = gbs_bmc_machine_class_init,
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},
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};
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@ -2766,6 +2766,8 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 1)
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static void virt_machine_6_0_options(MachineClass *mc)
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{
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virt_machine_6_1_options(mc);
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compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
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}
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DEFINE_VIRT_MACHINE(6, 0)
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@ -14,6 +14,7 @@
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qemu/main-loop.h"
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#include "trace.h"
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#include "gicv3_internal.h"
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@ -1357,7 +1358,9 @@ static void icc_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
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}
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break;
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default:
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g_assert_not_reached();
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: IRQ %d isn't active\n", __func__, irq);
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return;
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}
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icc_drop_prio(cs, grp);
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@ -2941,12 +2941,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
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static void armv7m_nvic_instance_init(Object *obj)
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{
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/* We have a different default value for the num-irq property
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* than our superclass. This function runs after qdev init
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* has set the defaults from the Property array and before
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* any user-specified property setting, so just modify the
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* value in the GICState struct.
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*/
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DeviceState *dev = DEVICE(obj);
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NVICState *nvic = NVIC(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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