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target/hppa: spelling fixes: Indicies, Truely

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Fixes: bb67ec32a0 "target/hppa: Include PSW_P in tb flags and mmu index"
Fixes: d7553f3591 "target/hppa: Populate an interval tree with valid tlb entries"
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Michael Tokarev 2023-11-14 19:09:54 +03:00
parent 51464c5612
commit 385b3280ce
2 changed files with 2 additions and 2 deletions
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2
target/hppa/cpu.h
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@ -56,7 +56,7 @@
1 << MMU_PL2_IDX | 1 << MMU_PL2_P_IDX | \ 1 << MMU_PL2_IDX | 1 << MMU_PL2_P_IDX | \
1 << MMU_USER_IDX | 1 << MMU_USER_P_IDX) 1 << MMU_USER_IDX | 1 << MMU_USER_P_IDX)
/* Indicies to flush for access_id changes. */ /* Indices to flush for access_id changes. */
#define HPPA_MMU_FLUSH_P_MASK \ #define HPPA_MMU_FLUSH_P_MASK \
(1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX | \ (1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX | \
1 << MMU_PL2_P_IDX | 1 << MMU_USER_P_IDX) 1 << MMU_PL2_P_IDX | 1 << MMU_USER_P_IDX)

2
target/hppa/machine.c
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@ -129,7 +129,7 @@ static int tlb_post_load(void *opaque, int version_id)
/* /*
* Re-create the interval tree from the valid entries. * Re-create the interval tree from the valid entries.
* Truely invalid entries should have start == end == 0. * Truly invalid entries should have start == end == 0.
* Otherwise it should be the in-flight tlb_partial entry. * Otherwise it should be the in-flight tlb_partial entry.
*/ */
for (uint32_t i = 0; i < ARRAY_SIZE(env->tlb); ++i) { for (uint32_t i = 0; i < ARRAY_SIZE(env->tlb); ++i) {