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https://github.com/Motorhead1991/qemu.git
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correct PCI ID for PREP PCI host bridge - added Grackle PCI host bridge
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1450 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
5457c8ceeb
commit
384d887691
1 changed files with 104 additions and 61 deletions
165
hw/pci.c
165
hw/pci.c
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@ -45,7 +45,9 @@ struct PCIBus {
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int devfn_min;
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int devfn_min;
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void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level);
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void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level);
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uint32_t config_reg; /* XXX: suppress */
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uint32_t config_reg; /* XXX: suppress */
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openpic_t *openpic; /* XXX: suppress */
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/* low level pic */
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SetIRQFunc *low_set_irq;
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void *irq_opaque;
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PCIDevice *devices[256];
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PCIDevice *devices[256];
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};
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};
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@ -723,25 +725,25 @@ PCIBus *pci_prep_init(void)
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PPC_PCIIO_write, s);
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PPC_PCIIO_write, s);
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cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
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cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
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d = pci_register_device(s, "PREP PCI Bridge", sizeof(PCIDevice), 0,
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/* PCI host bridge */
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NULL, NULL);
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d = pci_register_device(s, "PREP Host Bridge - Motorola Raven",
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sizeof(PCIDevice), 0, NULL, NULL);
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/* XXX: put correct IDs */
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d->config[0x00] = 0x57; // vendor_id : Motorola
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d->config[0x00] = 0x11; // vendor_id
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d->config[0x01] = 0x10;
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d->config[0x01] = 0x10;
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d->config[0x02] = 0x26; // device_id
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d->config[0x02] = 0x01; // device_id : Raven
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d->config[0x03] = 0x00;
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d->config[0x03] = 0x48;
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d->config[0x08] = 0x02; // revision
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d->config[0x08] = 0x00; // revision
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d->config[0x0a] = 0x04; // class_sub = pci2pci
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d->config[0x0A] = 0x00; // class_sub = pci host
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d->config[0x0b] = 0x06; // class_base = PCI_bridge
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d->config[0x0B] = 0x06; // class_base = PCI_bridge
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d->config[0x0e] = 0x01; // header_type
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d->config[0x0C] = 0x08; // cache_line_size
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d->config[0x0D] = 0x10; // latency_timer
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d->config[0x0E] = 0x00; // header_type
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d->config[0x34] = 0x00; // capabilities_pointer
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return s;
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return s;
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}
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}
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/* pmac pci init */
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#if 0
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/* Grackle PCI host */
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/* Grackle PCI host */
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static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
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static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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uint32_t val)
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@ -846,7 +848,93 @@ static CPUReadMemoryFunc *pci_grackle_read[] = {
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&pci_grackle_readw,
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&pci_grackle_readw,
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&pci_grackle_readl,
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&pci_grackle_readl,
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};
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};
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void pci_set_pic(PCIBus *bus, SetIRQFunc *set_irq, void *irq_opaque)
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{
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bus->low_set_irq = set_irq;
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bus->irq_opaque = irq_opaque;
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}
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/* XXX: we do not simulate the hardware - we rely on the BIOS to
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set correctly for irq line field */
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static void pci_set_irq_simple(PCIDevice *d, int irq_num, int level)
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{
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PCIBus *s = d->bus;
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s->low_set_irq(s->irq_opaque, d->config[PCI_INTERRUPT_LINE], level);
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}
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PCIBus *pci_grackle_init(uint32_t base)
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{
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PCIBus *s;
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PCIDevice *d;
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int pci_mem_config, pci_mem_data;
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s = pci_register_bus();
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s->set_irq = pci_set_irq_simple;
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pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,
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pci_grackle_config_write, s);
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pci_mem_data = cpu_register_io_memory(0, pci_grackle_read,
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pci_grackle_write, s);
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cpu_register_physical_memory(base, 0x1000, pci_mem_config);
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cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);
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d = pci_register_device(s, "Grackle host bridge", sizeof(PCIDevice),
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0, NULL, NULL);
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d->config[0x00] = 0x57; // vendor_id
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d->config[0x01] = 0x10;
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d->config[0x02] = 0x02; // device_id
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d->config[0x03] = 0x00;
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d->config[0x08] = 0x00; // revision
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d->config[0x09] = 0x01;
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d->config[0x0a] = 0x00; // class_sub = host
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d->config[0x0b] = 0x06; // class_base = PCI_bridge
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d->config[0x0e] = 0x00; // header_type
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d->config[0x18] = 0x00; // primary_bus
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d->config[0x19] = 0x01; // secondary_bus
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d->config[0x1a] = 0x00; // subordinate_bus
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d->config[0x1c] = 0x00;
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d->config[0x1d] = 0x00;
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d->config[0x20] = 0x00; // memory_base
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d->config[0x21] = 0x00;
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d->config[0x22] = 0x01; // memory_limit
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d->config[0x23] = 0x00;
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d->config[0x24] = 0x00; // prefetchable_memory_base
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d->config[0x25] = 0x00;
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d->config[0x26] = 0x00; // prefetchable_memory_limit
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d->config[0x27] = 0x00;
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#if 0
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/* PCI2PCI bridge same values as PearPC - check this */
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d->config[0x00] = 0x11; // vendor_id
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d->config[0x01] = 0x10;
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d->config[0x02] = 0x26; // device_id
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d->config[0x03] = 0x00;
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d->config[0x08] = 0x02; // revision
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d->config[0x0a] = 0x04; // class_sub = pci2pci
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d->config[0x0b] = 0x06; // class_base = PCI_bridge
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d->config[0x0e] = 0x01; // header_type
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d->config[0x18] = 0x0; // primary_bus
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d->config[0x19] = 0x1; // secondary_bus
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d->config[0x1a] = 0x1; // subordinate_bus
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d->config[0x1c] = 0x10; // io_base
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d->config[0x1d] = 0x20; // io_limit
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d->config[0x20] = 0x80; // memory_base
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d->config[0x21] = 0x80;
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d->config[0x22] = 0x90; // memory_limit
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d->config[0x23] = 0x80;
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d->config[0x24] = 0x00; // prefetchable_memory_base
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d->config[0x25] = 0x84;
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d->config[0x26] = 0x00; // prefetchable_memory_limit
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d->config[0x27] = 0x85;
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#endif
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#endif
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return s;
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}
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/* Uninorth PCI host (for all Mac99 and newer machines */
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/* Uninorth PCI host (for all Mac99 and newer machines */
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static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
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static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
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@ -1088,23 +1176,6 @@ static CPUReadMemoryFunc *pci_unin_read[] = {
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};
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};
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#endif
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#endif
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static void pmac_set_irq(PCIDevice *d, int irq_num, int level)
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{
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openpic_t *openpic;
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/* XXX: we do not simulate the hardware - we rely on the BIOS to
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set correctly for irq line field */
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openpic = d->bus->openpic;
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#ifdef TARGET_PPC
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if (openpic)
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openpic_set_irq(openpic, d->config[PCI_INTERRUPT_LINE], level);
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#endif
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}
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void pci_pmac_set_openpic(PCIBus *bus, openpic_t *openpic)
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{
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bus->openpic = openpic;
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}
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PCIBus *pci_pmac_init(void)
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PCIBus *pci_pmac_init(void)
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{
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{
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PCIBus *s;
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PCIBus *s;
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@ -1114,7 +1185,7 @@ PCIBus *pci_pmac_init(void)
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/* Use values found on a real PowerMac */
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/* Use values found on a real PowerMac */
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/* Uninorth main bus */
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/* Uninorth main bus */
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s = pci_register_bus();
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s = pci_register_bus();
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s->set_irq = pmac_set_irq;
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s->set_irq = pci_set_irq_simple;
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pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
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pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
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pci_unin_main_config_write, s);
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pci_unin_main_config_write, s);
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@ -1217,34 +1288,6 @@ PCIBus *pci_pmac_init(void)
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d->config[0x0E] = 0x00; // header_type
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d->config[0x0E] = 0x00; // header_type
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d->config[0x34] = 0x00; // capabilities_pointer
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d->config[0x34] = 0x00; // capabilities_pointer
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#endif
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#endif
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#if 0 // Grackle ?
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/* same values as PearPC - check this */
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d->config[0x00] = 0x11; // vendor_id
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d->config[0x01] = 0x10;
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d->config[0x02] = 0x26; // device_id
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d->config[0x03] = 0x00;
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d->config[0x08] = 0x02; // revision
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d->config[0x0a] = 0x04; // class_sub = pci2pci
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d->config[0x0b] = 0x06; // class_base = PCI_bridge
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d->config[0x0e] = 0x01; // header_type
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d->config[0x18] = 0x0; // primary_bus
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d->config[0x19] = 0x1; // secondary_bus
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d->config[0x1a] = 0x1; // subordinate_bus
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d->config[0x1c] = 0x10; // io_base
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d->config[0x1d] = 0x20; // io_limit
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d->config[0x20] = 0x80; // memory_base
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d->config[0x21] = 0x80;
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d->config[0x22] = 0x90; // memory_limit
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d->config[0x23] = 0x80;
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d->config[0x24] = 0x00; // prefetchable_memory_base
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d->config[0x25] = 0x84;
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d->config[0x26] = 0x00; // prefetchable_memory_limit
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d->config[0x27] = 0x85;
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#endif
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return s;
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return s;
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}
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}
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