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sh7750: convert memory controller/ioport to memory API

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Signed-off-by: Benoit Canet <benoit.canet@gmail.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Benoît Canet 2011-11-17 14:22:58 +01:00 • committed by Avi Kivity
parent a3d12d073e
commit 382863e2c6
4 changed files with 49 additions and 30 deletions
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72
hw/sh7750.c
View file

@ -30,10 +30,18 @@
#include "sh7750_regnames.h"
#include "sh_intc.h"
#include "cpu.h"
#include "exec-memory.h"
#define NB_DEVICES 4
typedef struct SH7750State {
MemoryRegion iomem;
MemoryRegion iomem_1f0;
MemoryRegion iomem_ff0;
MemoryRegion iomem_1f8;
MemoryRegion iomem_ff8;
MemoryRegion iomem_1fc;
MemoryRegion iomem_ffc;
/* CPU */
CPUSH4State *cpu;
/* Peripheral frequency in Hz */
@ -436,16 +444,16 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const sh7750_mem_read[] = {
sh7750_mem_readb,
sh7750_mem_readw,
sh7750_mem_readl
};
static CPUWriteMemoryFunc * const sh7750_mem_write[] = {
sh7750_mem_writeb,
sh7750_mem_writew,
sh7750_mem_writel
static const MemoryRegionOps sh7750_mem_ops = {
.old_mmio = {
.read = {sh7750_mem_readb,
sh7750_mem_readw,
sh7750_mem_readl },
.write = {sh7750_mem_writeb,
sh7750_mem_writew,
sh7750_mem_writel },
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
/* sh775x interrupt controller tables for sh_intc.c
@ -706,30 +714,40 @@ static CPUWriteMemoryFunc * const sh7750_mmct_write[] = {
sh7750_mmct_writel
};
SH7750State *sh7750_init(CPUSH4State * cpu)
SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
{
SH7750State *s;
int sh7750_io_memory;
int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */
s = g_malloc0(sizeof(SH7750State));
s->cpu = cpu;
s->periph_freq = 60000000; /* 60MHz */
sh7750_io_memory = cpu_register_io_memory(sh7750_mem_read,
sh7750_mem_write, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory_offset(0x1f000000, 0x1000,
sh7750_io_memory, 0x1f000000);
cpu_register_physical_memory_offset(0xff000000, 0x1000,
sh7750_io_memory, 0x1f000000);
cpu_register_physical_memory_offset(0x1f800000, 0x1000,
sh7750_io_memory, 0x1f800000);
cpu_register_physical_memory_offset(0xff800000, 0x1000,
sh7750_io_memory, 0x1f800000);
cpu_register_physical_memory_offset(0x1fc00000, 0x1000,
sh7750_io_memory, 0x1fc00000);
cpu_register_physical_memory_offset(0xffc00000, 0x1000,
sh7750_io_memory, 0x1fc00000);
memory_region_init_io(&s->iomem, &sh7750_mem_ops, s,
"memory", 0x1fc01000);
memory_region_init_alias(&s->iomem_1f0, "memory-1f0",
&s->iomem, 0x1f000000, 0x1000);
memory_region_add_subregion(sysmem, 0x1f000000, &s->iomem_1f0);
memory_region_init_alias(&s->iomem_ff0, "memory-ff0",
&s->iomem, 0x1f000000, 0x1000);
memory_region_add_subregion(sysmem, 0xff000000, &s->iomem_ff0);
memory_region_init_alias(&s->iomem_1f8, "memory-1f8",
&s->iomem, 0x1f800000, 0x1000);
memory_region_add_subregion(sysmem, 0x1f800000, &s->iomem_1f8);
memory_region_init_alias(&s->iomem_ff8, "memory-ff8",
&s->iomem, 0x1f800000, 0x1000);
memory_region_add_subregion(sysmem, 0xff800000, &s->iomem_ff8);
memory_region_init_alias(&s->iomem_1fc, "memory-1fc",
&s->iomem, 0x1fc00000, 0x1000);
memory_region_add_subregion(sysmem, 0x1fc00000, &s->iomem_1fc);
memory_region_init_alias(&s->iomem_ffc, "memory-ffc",
&s->iomem, 0x1fc00000, 0x1000);
memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc);
sh7750_mm_cache_and_tlb = cpu_register_io_memory(sh7750_mmct_read,
sh7750_mmct_write, s,