mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-03 07:43:54 -06:00
* Record-replay lockstep execution, log dumper and fixes (Alex, Pavel)
* SCSI fix to pass maximum transfer size (Daniel Barboza) * chardev fixes and improved iothread support (Daniel Berrangé, Peter) * checkpatch tweak (Eric) * make help tweak (Marc-André) * make more PCI NICs available with -net or -nic (myself) * change default q35 NIC to e1000e (myself) * SCSI support for NDOB bit (myself) * membarrier system call support (myself) * SuperIO refactoring (Philippe) * miscellaneous cleanups and fixes (Thomas) -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQEcBAABAgAGBQJapqaMAAoJEL/70l94x66DQoUH/Rvg+a8giz/SrEA4P8D3Cb2z 4GNbNUUoy4oU0ltD5IAMskMwpOsvl1batE0D+pKIlfO9NV4+Cj2kpgo0p9TxoYqM VCby3wRtx27zb5nVytC6M++iIKXmeEMqXmFw61I6umddNPSl4IR3hiHEE0DM+7dV UPIOvJeEiazyQaw3Iw+ZctNn8dDBKc/+6oxP9xRcYTaZ6hB4G9RZkqGNNSLcJkk7 R0UotdjzIZhyWMOkjIwlpTF4sWv8gsYUV4bPYKMYho5B0Obda2dBM3I1kpA8yDa/ xZ5lheOaAVBZvM5aMIcaQPa65MO9hLyXFmhMOgyfpJhLBBz6Qpa4OLLI6DeTN+0= =UAgA -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging * Record-replay lockstep execution, log dumper and fixes (Alex, Pavel) * SCSI fix to pass maximum transfer size (Daniel Barboza) * chardev fixes and improved iothread support (Daniel Berrangé, Peter) * checkpatch tweak (Eric) * make help tweak (Marc-André) * make more PCI NICs available with -net or -nic (myself) * change default q35 NIC to e1000e (myself) * SCSI support for NDOB bit (myself) * membarrier system call support (myself) * SuperIO refactoring (Philippe) * miscellaneous cleanups and fixes (Thomas) # gpg: Signature made Mon 12 Mar 2018 16:10:52 GMT # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (69 commits) tcg: fix cpu_io_recompile replay: update documentation replay: save vmstate of the asynchronous events replay: don't process async events when warping the clock scripts/replay-dump.py: replay log dumper replay: avoid recursive call of checkpoints replay: check return values of fwrite replay: push replay_mutex_lock up the call tree replay: don't destroy mutex at exit replay: make locking visible outside replay code replay/replay-internal.c: track holding of replay_lock replay/replay.c: bump REPLAY_VERSION again replay: save prior value of the host clock replay: added replay log format description replay: fix save/load vm for non-empty queue replay: fixed replay_enable_events replay: fix processing async events cpu-exec: fix exception_index handling hw/i386/pc: Factor out the superio code hw/alpha/dp264: Use the TYPE_SMC37C669_SUPERIO ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # default-configs/i386-softmmu.mak # default-configs/x86_64-softmmu.mak
This commit is contained in:
Peter Maydell
commit
3788c7b6e5
117 changed files with 1952 additions and 728 deletions
14
include/hw/char/parallel.h
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14
include/hw/char/parallel.h
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@ -0,0 +1,14 @@
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#ifndef HW_PARALLEL_H
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#define HW_PARALLEL_H
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#include "exec/memory.h"
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#include "hw/isa/isa.h"
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#include "chardev/char.h"
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void parallel_hds_isa_init(ISABus *bus, int n);
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bool parallel_mm_init(MemoryRegion *address_space,
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hwaddr base, int it_shift, qemu_irq irq,
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Chardev *chr);
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#endif
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@ -1,6 +1,10 @@
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#ifndef HW_I8257_H
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#define HW_I8257_H
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#include "hw/hw.h"
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#include "hw/isa/isa.h"
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#include "exec/ioport.h"
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#define TYPE_I8257 "i8257"
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typedef struct I8257Regs {
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@ -40,4 +44,6 @@ typedef struct I8257State {
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PortioList portio_pageh;
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} I8257State;
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void i8257_dma_init(ISABus *bus, bool high_page_enable);
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#endif
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@ -114,6 +114,7 @@ struct PCMachineClass {
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/* Device configuration: */
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bool pci_enabled;
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bool kvmclock_enabled;
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const char *default_nic_model;
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/* Compat options: */
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@ -151,14 +152,6 @@ struct PCMachineClass {
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#define PC_MACHINE_CLASS(klass) \
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OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
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/* parallel.c */
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void parallel_hds_isa_init(ISABus *bus, int n);
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bool parallel_mm_init(MemoryRegion *address_space,
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hwaddr base, int it_shift, qemu_irq irq,
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Chardev *chr);
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/* i8259.c */
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extern DeviceState *isa_pic;
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@ -196,15 +189,6 @@ void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
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void vmmouse_get_data(uint32_t *data);
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void vmmouse_set_data(const uint32_t *data);
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/* pckbd.c */
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#define I8042_A20_LINE "a20"
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void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
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MemoryRegion *region, ram_addr_t size,
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hwaddr mask);
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void i8042_isa_mouse_fake_event(void *opaque);
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void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out);
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/* pc.c */
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extern int fd_bootchk;
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@ -248,7 +232,7 @@ void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
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void pc_cmos_init(PCMachineState *pcms,
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BusState *ide0, BusState *ide1,
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ISADevice *s);
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void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
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void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus);
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void pc_pci_device_init(PCIBus *pci_bus);
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typedef void (*cpu_set_smm_t)(int smm, void *arg);
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24
include/hw/input/i8042.h
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24
include/hw/input/i8042.h
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@ -0,0 +1,24 @@
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/*
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* QEMU PS/2 Controller
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef HW_INPUT_I8042_H
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#define HW_INPUT_I8042_H
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#include "hw/hw.h"
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#include "hw/isa/isa.h"
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#define TYPE_I8042 "i8042"
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#define I8042_A20_LINE "a20"
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void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
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MemoryRegion *region, ram_addr_t size,
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hwaddr mask);
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void i8042_isa_mouse_fake_event(void *opaque);
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void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out);
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#endif /* HW_INPUT_I8042_H */
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@ -151,6 +151,4 @@ static inline ISABus *isa_bus_from_device(ISADevice *d)
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return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
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}
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/* i8257.c */
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void DMA_init(ISABus *bus, int high_page_enable);
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#endif
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@ -25,30 +25,20 @@
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#ifndef QEMU_PC87312_H
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#define QEMU_PC87312_H
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#include "hw/isa/isa.h"
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#include "hw/isa/superio.h"
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#define TYPE_PC87312 "pc87312"
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#define PC87312(obj) OBJECT_CHECK(PC87312State, (obj), TYPE_PC87312)
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#define TYPE_PC87312_SUPERIO "pc87312"
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#define PC87312(obj) OBJECT_CHECK(PC87312State, (obj), TYPE_PC87312_SUPERIO)
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typedef struct PC87312State {
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ISADevice dev;
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/*< private >*/
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ISASuperIODevice parent_dev;
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/*< public >*/
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uint32_t iobase;
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uint16_t iobase;
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uint8_t config; /* initial configuration */
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struct {
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ISADevice *dev;
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} parallel;
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struct {
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ISADevice *dev;
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} uart[2];
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struct {
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ISADevice *dev;
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} fdc;
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struct {
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ISADevice *dev;
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} ide;
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60
include/hw/isa/superio.h
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60
include/hw/isa/superio.h
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@ -0,0 +1,60 @@
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/*
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* Generic ISA Super I/O
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*
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* Copyright (c) 2018 Philippe Mathieu-Daudé
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*
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* This code is licensed under the GNU GPLv2 and later.
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* See the COPYING file in the top-level directory.
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HW_ISA_SUPERIO_H
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#define HW_ISA_SUPERIO_H
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#include "qemu-common.h"
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#include "sysemu/sysemu.h"
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#include "hw/isa/isa.h"
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#define TYPE_ISA_SUPERIO "isa-superio"
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#define ISA_SUPERIO(obj) \
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OBJECT_CHECK(ISASuperIODevice, (obj), TYPE_ISA_SUPERIO)
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#define ISA_SUPERIO_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ISASuperIOClass, (obj), TYPE_ISA_SUPERIO)
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#define ISA_SUPERIO_CLASS(klass) \
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OBJECT_CLASS_CHECK(ISASuperIOClass, (klass), TYPE_ISA_SUPERIO)
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typedef struct ISASuperIODevice {
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/*< private >*/
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ISADevice parent_obj;
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/*< public >*/
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ISADevice *parallel[MAX_PARALLEL_PORTS];
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ISADevice *serial[MAX_SERIAL_PORTS];
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ISADevice *floppy;
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ISADevice *kbc;
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ISADevice *ide;
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} ISASuperIODevice;
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typedef struct ISASuperIOFuncs {
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size_t count;
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bool (*is_enabled)(ISASuperIODevice *sio, uint8_t index);
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uint16_t (*get_iobase)(ISASuperIODevice *sio, uint8_t index);
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unsigned int (*get_irq)(ISASuperIODevice *sio, uint8_t index);
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unsigned int (*get_dma)(ISASuperIODevice *sio, uint8_t index);
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} ISASuperIOFuncs;
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typedef struct ISASuperIOClass {
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/*< private >*/
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ISADeviceClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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ISASuperIOFuncs parallel;
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ISASuperIOFuncs serial;
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ISASuperIOFuncs floppy;
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ISASuperIOFuncs ide;
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} ISASuperIOClass;
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#define TYPE_FDC37M81X_SUPERIO "fdc37m81x-superio"
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#define TYPE_SMC37C669_SUPERIO "smc37c669-superio"
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#endif /* HW_ISA_SUPERIO_H */
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@ -1,8 +1,10 @@
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#ifndef HW_VT82C686_H
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#define HW_VT82C686_H
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#define TYPE_VT82C686B_SUPERIO "vt82c686b-superio"
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/* vt82c686.c */
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ISABus *vt82c686b_init(PCIBus * bus, int devfn);
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ISABus *vt82c686b_isa_init(PCIBus * bus, int devfn);
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void vt82c686b_ac97_init(PCIBus *bus, int devfn);
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void vt82c686b_mc97_init(PCIBus *bus, int devfn);
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I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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@ -7,11 +7,6 @@
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/* esp.c */
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#define ESP_MAX_DEVS 7
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typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
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void esp_init(hwaddr espaddr, int it_shift,
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ESPDMAMemoryReadWriteFunc dma_memory_read,
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ESPDMAMemoryReadWriteFunc dma_memory_write,
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void *dma_opaque, qemu_irq irq, qemu_irq *reset,
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qemu_irq *dma_enable);
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#define ESP_REGS 16
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#define TI_BUFSZ 16
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@ -136,6 +131,11 @@ typedef struct {
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#define TCHI_FAS100A 0x4
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#define TCHI_AM53C974 0x12
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ESPState *esp_init(hwaddr espaddr, int it_shift,
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ESPDMAMemoryReadWriteFunc dma_memory_read,
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ESPDMAMemoryReadWriteFunc dma_memory_write,
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void *dma_opaque, qemu_irq irq, qemu_irq *reset,
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qemu_irq *dma_enable);
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void esp_dma_enable(ESPState *s, int irq, int level);
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void esp_request_cancelled(SCSIRequest *req);
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void esp_command_complete(SCSIRequest *req, uint32_t status, size_t resid);
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