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target/riscv: convert bare CPU models to RISCVCPUDef

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Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2025-02-06 17:10:46 +01:00
parent 198265df8a
commit 37815d80be
1 changed files with 17 additions and 41 deletions
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58
target/riscv/cpu.c
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@ -732,18 +732,6 @@ static void rv128_base_cpu_init(Object *obj)
}
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
static void rv64i_bare_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
riscv_cpu_set_misa_ext(env, RVI);
}
static void rv64e_bare_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
riscv_cpu_set_misa_ext(env, RVE);
}
#endif /* !TARGET_RISCV64 */
#if defined(TARGET_RISCV32) || \
@ -836,18 +824,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
cpu->cfg.ext_zicsr = true;
cpu->cfg.pmp = true;
}
static void rv32i_bare_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
riscv_cpu_set_misa_ext(env, RVI);
}
static void rv32e_bare_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
riscv_cpu_set_misa_ext(env, RVE);
}
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@ -3216,19 +3192,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
}, \
}
#define DEFINE_BARE_CPU(type_name, misa_mxl_max_, initfn) \
{ \
.name = (type_name), \
.parent = TYPE_RISCV_BARE_CPU, \
.instance_init = (initfn), \
.class_data = &(const RISCVCPUDef) { \
.misa_mxl_max = (misa_mxl_max_), \
.priv_spec = RISCV_PROFILE_ATTR_UNUSED, \
.vext_spec = RISCV_PROFILE_ATTR_UNUSED, \
.cfg.max_satp_mode = -1, \
}, \
}
#define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \
{ \
.name = (type_name), \
@ -3313,8 +3276,15 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_nommu_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cpu_init),
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, MXL_RV32, rv32i_bare_cpu_init),
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu_init),
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU,
.misa_mxl_max = MXL_RV32,
.misa_ext = RVI
),
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32E, TYPE_RISCV_BARE_CPU,
.misa_mxl_max = MXL_RV32,
.misa_ext = RVE
),
#endif
#if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
@ -3334,8 +3304,14 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init),
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu_init),
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu_init),
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64I, TYPE_RISCV_BARE_CPU,
.misa_mxl_max = MXL_RV64,
.misa_ext = RVI
),
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64E, TYPE_RISCV_BARE_CPU,
.misa_mxl_max = MXL_RV64,
.misa_ext = RVE
),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, TYPE_RISCV_CPU_RV64I, RVA22U64),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, TYPE_RISCV_CPU_RV64I, RVA22S64),