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target/riscv: Support mcycle/minstret write operation
mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Support mcycle/minstret through generic counter infrastructure. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220620231603.2547260-8-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Atish Patra
Alistair Francis
parent
621f35bb2f
commit
3780e33732
6 changed files with 215 additions and 55 deletions
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@ -21,6 +21,7 @@
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#include "qemu/log.h"
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#include "qemu/timer.h"
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#include "cpu.h"
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#include "pmu.h"
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#include "qemu/main-loop.h"
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#include "exec/exec-all.h"
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#include "sysemu/cpu-timers.h"
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@ -597,34 +598,28 @@ static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
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}
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/* User Timers and Counters */
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static RISCVException read_instret(CPURISCVState *env, int csrno,
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target_ulong *val)
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static target_ulong get_ticks(bool shift)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (icount_enabled()) {
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*val = icount_get();
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} else {
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*val = cpu_get_host_ticks();
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}
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#else
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*val = cpu_get_host_ticks();
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#endif
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return RISCV_EXCP_NONE;
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}
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int64_t val;
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target_ulong result;
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static RISCVException read_instreth(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (icount_enabled()) {
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*val = icount_get() >> 32;
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val = icount_get();
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} else {
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*val = cpu_get_host_ticks() >> 32;
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val = cpu_get_host_ticks();
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}
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#else
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*val = cpu_get_host_ticks() >> 32;
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val = cpu_get_host_ticks();
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#endif
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return RISCV_EXCP_NONE;
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if (shift) {
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result = val >> 32;
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} else {
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result = val;
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}
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return result;
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}
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#if defined(CONFIG_USER_ONLY)
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@ -642,11 +637,23 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
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return RISCV_EXCP_NONE;
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}
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static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = get_ticks(false);
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return RISCV_EXCP_NONE;
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}
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static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = get_ticks(true);
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return RISCV_EXCP_NONE;
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}
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#else /* CONFIG_USER_ONLY */
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static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val)
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{
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int evt_index = csrno - CSR_MHPMEVENT3;
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int evt_index = csrno - CSR_MCOUNTINHIBIT;
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*val = env->mhpmevent_val[evt_index];
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@ -655,7 +662,7 @@ static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val)
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static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
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{
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int evt_index = csrno - CSR_MHPMEVENT3;
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int evt_index = csrno - CSR_MCOUNTINHIBIT;
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env->mhpmevent_val[evt_index] = val;
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@ -664,55 +671,105 @@ static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
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static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val)
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{
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int ctr_index = csrno - CSR_MHPMCOUNTER3 + 3;
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int ctr_idx = csrno - CSR_MCYCLE;
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PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
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env->mhpmcounter_val[ctr_index] = val;
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counter->mhpmcounter_val = val;
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if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
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riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
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counter->mhpmcounter_prev = get_ticks(false);
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} else {
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/* Other counters can keep incrementing from the given value */
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counter->mhpmcounter_prev = val;
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}
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return RISCV_EXCP_NONE;
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}
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static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val)
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{
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int ctr_index = csrno - CSR_MHPMCOUNTER3H + 3;
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int ctr_idx = csrno - CSR_MCYCLEH;
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PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
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env->mhpmcounterh_val[ctr_index] = val;
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counter->mhpmcounterh_val = val;
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if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
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riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
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counter->mhpmcounterh_prev = get_ticks(true);
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} else {
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counter->mhpmcounterh_prev = val;
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}
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return RISCV_EXCP_NONE;
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}
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static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
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bool upper_half, uint32_t ctr_idx)
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{
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PMUCTRState counter = env->pmu_ctrs[ctr_idx];
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target_ulong ctr_prev = upper_half ? counter.mhpmcounterh_prev :
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counter.mhpmcounter_prev;
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target_ulong ctr_val = upper_half ? counter.mhpmcounterh_val :
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counter.mhpmcounter_val;
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if (get_field(env->mcountinhibit, BIT(ctr_idx))) {
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/**
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* Counter should not increment if inhibit bit is set. We can't really
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* stop the icount counting. Just return the counter value written by
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* the supervisor to indicate that counter was not incremented.
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*/
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if (!counter.started) {
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*val = ctr_val;
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return RISCV_EXCP_NONE;
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} else {
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/* Mark that the counter has been stopped */
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counter.started = false;
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}
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}
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/**
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* The kernel computes the perf delta by subtracting the current value from
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* the value it initialized previously (ctr_val).
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*/
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if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
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riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
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*val = get_ticks(upper_half) - ctr_prev + ctr_val;
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} else {
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*val = ctr_val;
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}
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return RISCV_EXCP_NONE;
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}
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static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
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{
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int ctr_index;
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uint16_t ctr_index;
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if (csrno >= CSR_MCYCLE && csrno <= CSR_MHPMCOUNTER31) {
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ctr_index = csrno - CSR_MHPMCOUNTER3 + 3;
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ctr_index = csrno - CSR_MCYCLE;
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} else if (csrno >= CSR_CYCLE && csrno <= CSR_HPMCOUNTER31) {
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ctr_index = csrno - CSR_HPMCOUNTER3 + 3;
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ctr_index = csrno - CSR_CYCLE;
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} else {
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return RISCV_EXCP_ILLEGAL_INST;
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}
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*val = env->mhpmcounter_val[ctr_index];
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return RISCV_EXCP_NONE;
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return riscv_pmu_read_ctr(env, val, false, ctr_index);
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}
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static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
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{
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int ctr_index;
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uint16_t ctr_index;
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if (csrno >= CSR_MCYCLEH && csrno <= CSR_MHPMCOUNTER31H) {
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ctr_index = csrno - CSR_MHPMCOUNTER3H + 3;
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ctr_index = csrno - CSR_MCYCLEH;
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} else if (csrno >= CSR_CYCLEH && csrno <= CSR_HPMCOUNTER31H) {
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ctr_index = csrno - CSR_HPMCOUNTER3H + 3;
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ctr_index = csrno - CSR_CYCLEH;
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} else {
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return RISCV_EXCP_ILLEGAL_INST;
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}
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*val = env->mhpmcounterh_val[ctr_index];
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return RISCV_EXCP_NONE;
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return riscv_pmu_read_ctr(env, val, true, ctr_index);
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}
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static RISCVException read_time(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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@ -1567,11 +1624,23 @@ static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
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static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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int cidx;
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PMUCTRState *counter;
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if (env->priv_ver < PRIV_VERSION_1_11_0) {
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return RISCV_EXCP_ILLEGAL_INST;
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}
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env->mcountinhibit = val;
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/* Check if any other counter is also monitoring cycles/instructions */
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for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) {
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if (!get_field(env->mcountinhibit, BIT(cidx))) {
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counter = &env->pmu_ctrs[cidx];
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counter->started = true;
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}
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}
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return RISCV_EXCP_NONE;
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}
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@ -3533,10 +3602,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_VLENB] = { "vlenb", vs, read_vlenb,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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/* User Timers and Counters */
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[CSR_CYCLE] = { "cycle", ctr, read_instret },
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[CSR_INSTRET] = { "instret", ctr, read_instret },
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[CSR_CYCLEH] = { "cycleh", ctr32, read_instreth },
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[CSR_INSTRETH] = { "instreth", ctr32, read_instreth },
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[CSR_CYCLE] = { "cycle", ctr, read_hpmcounter },
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[CSR_INSTRET] = { "instret", ctr, read_hpmcounter },
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[CSR_CYCLEH] = { "cycleh", ctr32, read_hpmcounterh },
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[CSR_INSTRETH] = { "instreth", ctr32, read_hpmcounterh },
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/*
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* In privileged mode, the monitor will have to emulate TIME CSRs only if
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@ -3550,10 +3619,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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#if !defined(CONFIG_USER_ONLY)
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/* Machine Timers and Counters */
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[CSR_MCYCLE] = { "mcycle", any, read_instret },
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[CSR_MINSTRET] = { "minstret", any, read_instret },
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[CSR_MCYCLEH] = { "mcycleh", any32, read_instreth },
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[CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
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[CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, write_mhpmcounter},
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[CSR_MINSTRET] = { "minstret", any, read_hpmcounter, write_mhpmcounter},
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[CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh, write_mhpmcounterh},
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[CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh, write_mhpmcounterh},
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/* Machine Information Registers */
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[CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
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