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ahci: Add allwinner AHCI

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Add a Sysbus AHCI subclass for the Allwinner AHCI. It has a few extra
vendor specific registers which are used for phy and power init.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: 833b5b05ed5ade38bf69656679b0a7575e79492b.1445917756.git.crosthwaite.peter@gmail.com
[resolved patch context on pull --js]
Signed-off-by: John Snow <jsnow@redhat.com>
This commit is contained in:
Peter Crosthwaite 2015-11-06 14:09:01 -05:00 • committed by John Snow
parent 0487eea48e
commit 377e214539
3 changed files with 112 additions and 0 deletions
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95
hw/ide/ahci.c
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@ -1690,9 +1690,104 @@ static const TypeInfo sysbus_ahci_info = {
.class_init = sysbus_ahci_class_init,
};
#define ALLWINNER_AHCI_BISTAFR ((0xa0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_BISTCR ((0xa4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_BISTFCTR ((0xa8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_BISTSR ((0xac - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_BISTDECR ((0xb0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_DIAGNR0 ((0xb4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_DIAGNR1 ((0xb8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_OOBR ((0xbc - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_PHYCS0R ((0xc0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_PHYCS1R ((0xc4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_PHYCS2R ((0xc8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_TIMER1MS ((0xe0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_GPARAM1R ((0xe8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_GPARAM2R ((0xec - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_PPARAMR ((0xf0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_TESTR ((0xf4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_VERSIONR ((0xf8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_IDR ((0xfc - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_RWCR ((0xfc - ALLWINNER_AHCI_MMIO_OFF) / 4)
static uint64_t allwinner_ahci_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
AllwinnerAHCIState *a = opaque;
uint64_t val = a->regs[addr/4];
switch (addr / 4) {
case ALLWINNER_AHCI_PHYCS0R:
val |= 0x2 << 28;
break;
case ALLWINNER_AHCI_PHYCS2R:
val &= ~(0x1 << 24);
break;
}
DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
addr, val, size);
return val;
}
static void allwinner_ahci_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
AllwinnerAHCIState *a = opaque;
DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
addr, val, size);
a->regs[addr/4] = val;
}
static const MemoryRegionOps allwinner_ahci_mem_ops = {
.read = allwinner_ahci_mem_read,
.write = allwinner_ahci_mem_write,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void allwinner_ahci_init(Object *obj)
{
SysbusAHCIState *s = SYSBUS_AHCI(obj);
AllwinnerAHCIState *a = ALLWINNER_AHCI(obj);
memory_region_init_io(&a->mmio, OBJECT(obj), &allwinner_ahci_mem_ops, a,
"allwinner-ahci", ALLWINNER_AHCI_MMIO_SIZE);
memory_region_add_subregion(&s->ahci.mem, ALLWINNER_AHCI_MMIO_OFF,
&a->mmio);
}
static const VMStateDescription vmstate_allwinner_ahci = {
.name = "allwinner-ahci",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, AllwinnerAHCIState,
ALLWINNER_AHCI_MMIO_SIZE/4),
VMSTATE_END_OF_LIST()
}
};
static void allwinner_ahci_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_allwinner_ahci;
}
static const TypeInfo allwinner_ahci_info = {
.name = TYPE_ALLWINNER_AHCI,
.parent = TYPE_SYSBUS_AHCI,
.instance_size = sizeof(AllwinnerAHCIState),
.instance_init = allwinner_ahci_init,
.class_init = allwinner_ahci_class_init,
};
static void sysbus_ahci_register_types(void)
{
type_register_static(&sysbus_ahci_info);
type_register_static(&allwinner_ahci_info);
}
type_init(sysbus_ahci_register_types)