motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-06 09:13:55 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/xtensa updates for v6.1:

Browse source 
- don't generate extra EXCP_DEBUG on exception
 - fix l32ex access ring
 - clean up unaligned access
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCgAxFiEEK2eFS5jlMn3N6xfYUfnMkfg/oEQFAmCnvMITHGpjbXZia2Jj
 QGdtYWlsLmNvbQAKCRBR+cyR+D+gRHCVEACR5nXm21Y7Jc9R+Pkpe5rd8xyw5J/m
 2PKM8uAH6XSo/DGanuzXUW345NmVbpL0DWSmWI6WQ7LfXpqgkO/UM76DeZGrWlTB
 lqQXTbVBv+crkYmxFlnYAaoVYEmSZb900RaKyFiWG95edjV/YoPnq6qzT8Xy3N6K
 jYRGh+cWnzxTLCsscEK8DySA79yox+Kw+49gmHddXdjhwYDs0ekT3cGhQyK8vlTU
 Zpu7tVwQvE3SxwSgNDrg5eG12dLTfnfLrE/wFAyQdlDUTNxjpF36mvWKUm9BmnNT
 L8AedMMbdqH2+0gcFfetoVOcSmquDT4axiQq/eCaudBqUzhBncaDEHeXZVpMoADI
 +Je5awz9pr0JStPvMANfpczRmf3WrD/de9olwRYfSZmaZ0O1w0RV8SAa4/9YPpHl
 H0B5bNN9fl69nGdM6Nm+ERp2evrk2qnqH9/TXJC/waU7QphbkGC2MO5BmKjRNyWj
 7hxWTAW1R5/BJLgFIEkuVkVV8G6a+Jz17olhGKiXgWTJORBQE9ACWmOK/A17Nh09
 LUX0nTA5eVWUgV78P599naT0Xx6SLK9QHUw6tZs3US3hrZDQvjmrrxFsf1b6qaF/
 1D0XRQlqxdEZvdgvqJcW0AlMz2eFx1/vjgHPzVbHK7L4sA6XK2UFskuttgk2g9m9
 8Ro/rH/zK6Qgmw==
 =fLOY
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/xtensa/tags/20210521-xtensa' into staging

target/xtensa updates for v6.1:

- don't generate extra EXCP_DEBUG on exception
- fix l32ex access ring
- clean up unaligned access

# gpg: Signature made Fri 21 May 2021 14:59:30 BST
# gpg:                using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg:                issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20210521-xtensa:
  target/xtensa: clean up unaligned access
  target/xtensa: fix access ring in l32ex
  target/xtensa: don't generate extra EXCP_DEBUG on exception

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-05-24 12:00:33 +01:00
commit 371ebfe286
10 changed files with 289 additions and 90 deletions
Download patch file Download diff file Expand all files Collapse all files

221
tests/tcg/xtensa/test_load_store.S Normal file
View file

@ -0,0 +1,221 @@
#include "macros.inc"
test_suite load_store
.macro load_ok_test op, type, data, value
.data
.align 4
1:
\type \data
.previous
reset_ps
set_vector kernel, 0
movi a3, 1b
addi a4, a4, 1
mov a5, a4
\op a5, a3, 0
movi a6, \value
assert eq, a5, a6
.endm
#if XCHAL_UNALIGNED_LOAD_EXCEPTION
.macro load_unaligned_test will_trap, op, type, data, value
.data
.align 4
.byte 0
1:
\type \data
.previous
reset_ps
.ifeq \will_trap
set_vector kernel, 0
.else
set_vector kernel, 2f
.endif
movi a3, 1b
addi a4, a4, 1
mov a5, a4
1:
\op a5, a3, 0
.ifeq \will_trap
movi a6, \value
assert eq, a5, a6
.else
test_fail
2:
rsr a6, exccause
movi a7, 9
assert eq, a6, a7
rsr a6, epc1
movi a7, 1b
assert eq, a6, a7
rsr a6, excvaddr
assert eq, a6, a3
assert eq, a5, a4
.endif
reset_ps
.endm
#else
.macro load_unaligned_test will_trap, op, type, data, value
.data
.align 4
1:
\type \data
.previous
reset_ps
set_vector kernel, 0
movi a3, 1b + 1
addi a4, a4, 1
mov a5, a4
\op a5, a3, 0
movi a6, \value
assert eq, a5, a6
.endm
#endif
.macro store_ok_test op, type, value
.data
.align 4
.byte 0, 0, 0, 0x55
1:
\type 0
2:
.byte 0xaa
.previous
reset_ps
set_vector kernel, 0
movi a3, 1b
movi a5, \value
\op a5, a3, 0
movi a3, 2b
l8ui a5, a3, 0
movi a6, 0xaa
assert eq, a5, a6
movi a3, 1b - 1
l8ui a5, a3, 0
movi a6, 0x55
assert eq, a5, a6
.endm
#if XCHAL_UNALIGNED_STORE_EXCEPTION
.macro store_unaligned_test will_trap, op, nop, type, value
.data
.align 4
.byte 0x55
1:
\type 0
2:
.byte 0xaa
.previous
reset_ps
.ifeq \will_trap
set_vector kernel, 0
.else
set_vector kernel, 4f
.endif
movi a3, 1b
movi a5, \value
3:
\op a5, a3, 0
.ifne \will_trap
test_fail
4:
rsr a6, exccause
movi a7, 9
assert eq, a6, a7
rsr a6, epc1
movi a7, 3b
assert eq, a6, a7
rsr a6, excvaddr
assert eq, a6, a3
l8ui a5, a3, 0
assert eqi, a5, 0
.endif
reset_ps
movi a3, 2b
l8ui a5, a3, 0
movi a6, 0xaa
assert eq, a5, a6
movi a3, 1b - 1
l8ui a5, a3, 0
movi a6, 0x55
assert eq, a5, a6
.endm
#else
.macro store_unaligned_test will_trap, sop, lop, type, value
.data
.align 4
.byte 0x55
1:
\type 0
.previous
reset_ps
set_vector kernel, 0
movi a3, 1b
movi a5, \value
\sop a5, a3, 0
movi a3, 1b - 1
\lop a6, a3, 0
assert eq, a5, a6
.endm
#endif
test load_ok
load_ok_test l16si, .short, 0x00001234, 0x00001234
load_ok_test l16si, .short, 0x000089ab, 0xffff89ab
load_ok_test l16ui, .short, 0x00001234, 0x00001234
load_ok_test l16ui, .short, 0x000089ab, 0x000089ab
load_ok_test l32i, .word, 0x12345678, 0x12345678
#if XCHAL_HAVE_RELEASE_SYNC
load_ok_test l32ai, .word, 0x12345678, 0x12345678
#endif
test_end
#undef WILL_TRAP
#if XCHAL_UNALIGNED_LOAD_HW
#define WILL_TRAP 0
#else
#define WILL_TRAP 1
#endif
test load_unaligned
load_unaligned_test WILL_TRAP, l16si, .short, 0x00001234, 0x00001234
load_unaligned_test WILL_TRAP, l16si, .short, 0x000089ab, 0xffff89ab
load_unaligned_test WILL_TRAP, l16ui, .short, 0x00001234, 0x00001234
load_unaligned_test WILL_TRAP, l16ui, .short, 0x000089ab, 0x000089ab
load_unaligned_test WILL_TRAP, l32i, .word, 0x12345678, 0x12345678
#if XCHAL_HAVE_RELEASE_SYNC
load_unaligned_test 1, l32ai, .word, 0x12345678, 0x12345678
#endif
test_end
test store_ok
store_ok_test s16i, .short, 0x00001234
store_ok_test s32i, .word, 0x12345678
#if XCHAL_HAVE_RELEASE_SYNC
store_ok_test s32ri, .word, 0x12345678
#endif
test_end
#undef WILL_TRAP
#if XCHAL_UNALIGNED_STORE_HW
#define WILL_TRAP 0
#else
#define WILL_TRAP 1
#endif
test store_unaligned
store_unaligned_test WILL_TRAP, s16i, l16ui, .short, 0x00001234
store_unaligned_test WILL_TRAP, s32i, l32i, .word, 0x12345678
#if XCHAL_HAVE_RELEASE_SYNC
store_unaligned_test 1, s32ri, l32i, .word, 0x12345678
#endif
test_end
test_suite_end